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1/72 stlc1502 august 2004 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 1 main features hcmos7 technology power supply: core 2.5 v and i/o: 3.3 v industry standard 32-bit risc microprocessor (arm7/tdmi core) 16-bit, fixed point 100 mips dsp (d950) 2 10/100 base-t ethernet macs vlan support jtag smart power management 2 general description stmicroelectronics? stlc1502 is a high perfor- mance voip processor specially targeted for the time effective design of ip-phones and analog gateway applications bundled with a comprehen- sive embedded software solution. when used in the enterprise lan ip phone space, this device enables the augmentation and replace- ment of traditional telephone systems with net- work based communications systems running over local and wide area ip networks. to design an ip phone, the only other parts required will be an analog interface, some optional flash memory for upgradable software and fast ethernet physi- cal layer devices. the st complete ip phone ref- erence design includes standards compliant application programming interfaces (apis), proto- col management software and software develop- ment tools. the stlc1502 also has all the proper interfaces to be a cost effective solution for small gateway applications. st also offer a complete sw refer- ence design for small gateway applications. hence, the stlc1502 enables a superior and cost effective platform development for ip-phones as well as voice gateway applications, providing de- velopers with a low risk, rapid time to market solu- tion. the stlc1502 integrates low power d950 dsp with a arm7/tdmi mcu and two ethernet 10/100 base-t media access control interfaces. 3 reference software features 3.1 arm7/tdmi industry standard real time os: vxworks network protocol stack tcp/ip, udp, tftp, dhcp, http server ethernet/pc communication drivers high level chip control stack management ? snmp (optional) ? application specific mibs signalling protocol mgcp, h.323 (including h.450), sip 3.2 d950 voice codec unit (vcu) g.711 packetized pcm g.729ab, 8kbps cs-acelp g.726, 16-40 kbps adpcm g.723.1a, 6.3/5.3 kbps mp-mlq encoding and decoding of pcm sample frames packing/unpacking of compressed information in codewords fax modem : t.38 fax relay, v.21, v.17, v.27ter and v.29 fax datapump data modem: v.34 datapump rate selection high performance voice activity detector comfort noise generator (cng) g.165 32 ms line & acoustic echo canceller low latency system implementation preliminary data voice over ip processor rev. 2 figure 1. package t able 1. order codes part number package STLC1502D pqfp208 stlc1502p pqfp208 pqfp208
stlc1502 2/72 table of contents 1 main features ................................................................................................................. .............1 2 general description........................................................................................................... .................1 3 reference software features ................................................................................................... .........1 3.1 arm7/tdmi ................................................................................................................... ..........1 3.2 d950 voice codec unit (vcu)................................................................................................. 1 4 block diagram................................................................................................................. ....................4 5 system overview ............................................................................................................... ................4 5.1 arm7 domain ................................................................................................................. .........4 5.2 d950 domain................................................................................................................. ...........5 5.3 clocks ...................................................................................................................... ................5 5.4 reset scheme ................................................................................................................ ..........6 6 pin descriptions .............................................................................................................. ...................6 6.1 pin description table ....................................................................................................... ........7 7 arm memory configuration ...................................................................................................... .......12 7.1 arm memory map .............................................................................................................. ...12 8 ahb bus....................................................................................................................... ....................13 8.1 internal ram ................................................................................................................ ..........13 8.2 esm interface............................................................................................................... ..........13 8.2.1 esm register map [0x0c600000]....................................................................................15 8.3 edm interface ............................................................................................................... .........15 8.3.1 edm register map [0x0c580000]....................................................................................18 8.4 dma controller.............................................................................................................. .........21 8.5 ethernet dma-macs........................................................................................................... ...21 8.5.1 the dma descriptors chain.............................................................................................21 8.5.2 the descriptor control bits ............................................................................................... 22 8.5.3 transfer interrupts ....................................................................................................... .....22 8.5.4 frames transmission (tx) ................................................................................................22 8.5.5 open list approach ........................................................................................................ ...22 8.5.6 closed list approach...................................................................................................... ...23 8.5.7 frames reception (rx) ..................................................................................................... 23 8.5.8 ethernet block register map [0x0c680000].....................................................................24 8.6 arbiter..................................................................................................................... ................27 8.7 tic-test interface controller............................................................................................... ...28 8.8 ahb-asb bridge .............................................................................................................. ......28 9 apb bus ....................................................................................................................... ....................28 9.1 timer....................................................................................................................... ...............30 9.1.1 timer introduction........................................................................................................ .....30 9.1.2 timer operation ........................................................................................................... .....30 9.1.3 timer register map [0x0c000000] ....................................................................................32 9.2 watchdog timer.............................................................................................................. .......33 9.2.1 watch dog register map [0x0c500000] ..........................................................................33 9.3 miscellaneous i/o........................................................................................................... ........33 9.3.1 miscellaneous register map [0x0c080000] .....................................................................33 9.4 interrupt controller ........................................................................................................ .........34 9.4.1 interrupt control ......................................................................................................... .......34 9.4.2 interrupt control scheme.................................................................................................. .35 9.4.3 interrupt register map [0x0c100000]................................................................................36 9.5 spi-serial peripheral interface............................................................................................. ..37 9.6 main features ............................................................................................................... .........38 9.6.1 programming procedure...................................................................................................38
3/72 stlc1502 9.6.2 data transfer format ...................................................................................................... .39 9.6.3 collision management ...................................................................................................... 39 9.6.4 spi register map [0x0c280000] .......................................................................................40 9.7 i2c bus interface ........................................................................................................... .........40 9.7.1 main features ............................................................................................................. .....40 9.7.2 general description....................................................................................................... ...40 9.7.3 functional description.................................................................................................... ..42 9.7.4 i2c registers map [0x0c300000] .....................................................................................45 9.8 uart-universal asynchronous receiver transmitter ...........................................................45 9.8.1 operation................................................................................................................. .........45 9.8.2 baud rate generation...................................................................................................... ..46 9.8.3 the timeout interrupt ..................................................................................................... ...47 9.8.4 interrupt control ......................................................................................................... .......47 9.8.5 uart memory map..........................................................................................................4 7 9.9 gpio/keypad encoder ......................................................................................................... ..48 9.9.1 gpio operation mode ......................................................................................................4 8 9.9.2 keyboard operation mode ................................................................................................48 9.9.3 gpio registers map [0x0c400000] ..................................................................................48 9.10 hpi (*) .................................................................................................................... ................49 9.10.1 send message from host processor to arm...................................................................50 9.10.2 receive message from arm by host processor .............................................................50 9.10.3 send message from arm to host processor...................................................................50 9.10.4 receive message from host processor by arm .............................................................50 9.10.5 hpi memory map ........................................................................................................... ..51 9.11 dual port sram............................................................................................................. ........51 9.11.1 dpram protocol........................................................................................................... ....51 9.11.2 dual port memory map [0x0c180000] .............................................................................53 9.11.3 dpram registers map...................................................................................................... 54 10 stlc1502 register map........................................................................................................ ..........54 11 d950 domain .................................................................................................................. .................57 11.1 d950 memory map............................................................................................................ .....58 11.2 dpram memory map [0x8000] .............................................................................................59 12 pcm interface ................................................................................................................ ..................60 12.1 miscellaneous interface .................................................................................................... .....61 12.2 interrupt event management................................................................................................. .61 12.3 clock distribution ......................................................................................................... ..........62 12.4 reset distribution and configuration .....................................................................................62 12.5 data flow management....................................................................................................... ..62 12.6 basic operation............................................................................................................ ..........62 12.7 pcm coding voice frame ..................................................................................................... .63 12.7.1 linear coding voice frame ..............................................................................................63 12.8 pcm register list .......................................................................................................... ........63 13 electrical specifications and timings ........................................................................................ .......65
stlc1502 4/72 4 block diagram figure 2. block diagram 5 system overview two main blocks can be i dentified in the device architecture: arm domain and the d950 domain 5.1 arm7 domain the arm domain is a multibus microprocessor system based on the arm7tdmi processor. the system bus is based on the advanced microcontroller bus architecture (amba) that includes two distinct buses: the advanced high performance bus (ahb) for high performances system modules the advanced peripheral bus ( apb) for low power peri pherals. a high speed 32 bit data bus is provided to connect external memories. a controller for external static memory (esm) and a controller for external dynamic memory (edm) are provided. static memories, like flash eprom, sram and dynamic memories like edo, sdram, can be connected on the same external 32 bits high speed bus two mac cores provide ethernet frames mac layer processing capability. each mac core has an associated dmac for transfer of ethernet frames to/from arm7 main memory two mii interfaces can hook directly to two 10/100 ethernet phys standard serial communication ports are available for easy device connection the spi port is mainly dedicated to the codec control. it is compatible with the stm codecs stlc5046, stlc5048, stw5093. it is a standard spi port and other peripherals can be connected to it beside the codec i2c port can be use to connect a lcd driver in case of ip-phone application, and a serial eeprom
5/72 stlc1502 for boot coded and configuration data storage gpio block includes as an alternative function a scanning key encoder for direct interface with a 6x6 keypad matrix debouncing function is performed, so no overhead for the arm controller is introduced uart port allows connection to a host terminal. code downloaded through uart can be performed during boot a host processor interface (*) (hpi) allows direct connection of an external control processor. the interface is directly compatible with the motorola mpc850 external bus (*) note: hpi interface is available only on request 5.2 d950 domain the d950 domain is a dsp machine based on the d950 core. the d950 core is based on harvard architecture with separate buses for instruction (i-bus) and data (x-bus, y-bus) the internal rom runs basic system management code and standard vocoders like g711,g723.1a,g729ab and others. additional vocoders and algorithms are downloaded from the arm side through the dpram external codec is connected with a standard four wires pcm bus interface jtag and emulation port are available for system software/hardware testing dpram is used as a communication channel between the arm and d950 control messages and voice packets are exchanged through the dpcom fax over ip support 5.3 clocks three main clock domains are present: d950 and peripherals (100 mhz max) arm7 and peripherals (60 mhz max) pcm (8.192 mhz max) the clock base is provided by a fixed external 25mhz crystal/oscillator. a 25mhz clock output can be used as a master clock for external ethernet phy devices, in 10baset operation. note: for 100baset operation, this clock may not be sufficiently stable with tight jitter requirements. thus the phy?s may need their own 25 mhz crystal. internal pll?s provide independent clocks to the d950 and arm7 domain. the arm frequency is set by external pin, that selects between 50 mhz and 60 mhz. the d950 frequency can be set by the arm via status register programming. four possible values are provided: 100 mhz 180 mhz 190 mhz 200 mhz to change the d950 master clock frequency the following procedure must be followed: 1) disable the d950 clock, by resetting the dclk bit in the control register of the misc control register. 2) wait 10 arm cycles 3) select a new d950 master clock, by writing the misc status register. 4) wait 4 ms 5) disable the d950 clock, by setting the dclk bit in the misc control register. an internal divider provides an internal pcm clock, 2083 khz, that is not exactly the standard 2048 khz. ? an external pcm clock frequency can be applied using a dedicated crystal or oscillator, to provide ex-
stlc1502 6/72 actly 8khz synch and sampling clock on the pcm bus. (external pins configuration testsel[3:0] at [0011]). the pcm clock rate can be selected via software to achieve the following values: 1536 (24 ch.) 2048 (32 ch.) 4096 (64 ch.) 8192 khz (128 ch.). ? the pcm clock and frame synch signals can be selected as inputs or outputs, by programming the con- trol register in the miscellaneous block. 5.4 reset scheme a general hardware reset is provided by an external pin and is generated during power-on. ? three blocks are reset by the general reset: arm7 core, d950 core, pcm interface. ? the watchdog timer can generate a reset of the arm7 core, as well. ? a software reset is available for each of the blocks in the control register. the following reset hierarchy should be implemented in order to provide a reliable start-up. they are list- ed in the order of propagation thus it follows that when an arm7 reset is generated, a d950 reset and a pcm reset are also generated and further, when a d950 reset is generated a pcm reset is also generated: 1) hw reset (pin and power-on) 2) watchdog timer 3) arm7 software reset 4) d950 reset 5) pcm block reset 6 pin descriptions the stlc1502 will be delivered in: pqfp 208 pins
7/72 stlc1502 figure 3. 208-pin pqfp 6.1 pin description table table 2. pin description pin pin name pin description/note pin drive pin type clocks, reset 41 xtalin 25 mhz crystal input master clock or dsp clock in pll bypass mode i 42 xtalout 25 mhz crystal feedback o 43 pxtalin 8.192 mhz crystal input pcm i/f clock or pcm input clock in pll bypass mode i 44 pxtalout 8.192 mhz crystal feedback o 45 edmiclk sdram feedback clock (input) 8ma i/o
stlc1502 8/72 46 testarmclk arm clock in bypass mode i 52 selarmfreq selects arm pii vco frequency i 53 rstn asynchronous master reset input i 188 clkout 25mhz master clock out 4ma o miscellaneous 47 bootsel_treqa boot selection: select internal [1] or external [0] booting rom. if proper test configuration has been selected, then signal assumes tic request a functionality i 118 hpisel select between hpi[1] or gpio_kbd if [0] i memory i/f (shared signals) 125, 126, 127, 129, 130, 131, 133, 134, 135, 136, 137, 138, 140, 141 add[0..13] memory address bus. for dynamic ram, they are the whole address, whereas for static, they are the lsbits addresses. at power up or hardware reset all address values are 0 4ma o 62, 63, 64, 65, 66, 69, 70, 71, 72, 73, 74, 75, 77, 78, 79, 81, 82, 84, 85, 86, 88, 89, 91, 92, 93, 95, 96, 98, 99, 100, 102, 103 data[0..31] memory data bus, to exchange data between memory controller and external memories 8ma i/o 2, 3, 4, 5 wenbsn[0..3] write byte enable for external static ram or byte strobe for dynamic external ram 8ma o 6 oen output enable for static/dynamic external ram. at power up or hardware reset, the signal will be asserted if the external booting (bootsel = ?1?) has been selected 8ma o esm (specific controls) 142, 144, 145, 146, 148, 149, 150, 152 add[14..21] memory address bus? msbits. they complete the esm addressability. a total of 4mbyte external (flash/ sram) address space is addressed by the stlc1502 device. at the first fetch of instruction after power_up or hardware reset, all address values are ?0? 4ma o 153, 154, 155 esmcs[0..2]n chip select [0..2] for external memory (flash/sram). at power up or hardware reset, if external boot rom has been selected, (bootsel =?1?) the signal is asserted during the fetch instruction, else the selection depends on internal address mapping 4ma o 61 ecs0width external flash/sram data bus size: if settled to ?l?, select a 8 bit parallelism data. i table 2. pin description (continued) pin pin name pin description/note pin drive pin type
9/72 stlc1502 edm ( specific controls) 156, 158, 159, 160 edmcsn[0..3] chip select for sdram or ras for edo dram 8ma o 161 edmclken sdram clock enable 8ma o 162 edmoclk sdram output clock 8ma o 165 edmras sdram ras command 8ma o 166 edmcas sdram cas command 8ma o 167 edmwe sdram we command 8ma o mii interface port # 1 168 mii1_txen transmit enable 4ma o 169 mii1_txclk transmit clock reference for txd, txen, txer i 170, 171, 174, 175 mii1_txd[0..3] transmit data bus 4ma o 176 mii1_rxclk receive clock reference for rxd, rxdv, rxer i 177 mii1_rxdv receive data valid i 178 mii1_rxer receive error signal, indicates an error condition on receiving data i 181, 182, 183, 184 mii1_rxd[0..3] receive data bus i 185 mii1_col collision signal i 186 mii1_crs carrier sense indication i mii interface port # 2 193 mii2_txclk transmit clock reference for txd, txen, txer i 194 mii2_txen transmit enable 4ma o 195, 196, 197, 198 mii2_txd[0..3] transmit data bus 4ma o 200 mii2_rxclk receive clock reference for rxd, rxdv, rxer i 201 mii2_rxdv receive data valid i 202 mii2_rxer receive error signal, indicates an error condition on receiving data i 203, 204, 205, 206 mii2_rxd[0..3] receive data bus i 207 mii2_col collision signal i 208 mii2_crs carrier sense indication i phy i/f management 189 mdc mii management clock 4ma o 190 mdio mii management data i/o 4ma i/o uart i/f 112 sin serial data input i 113 sout serial data output 2ma o i2c i/f 116 scl i2c clock 2ma i/o 117 sda i2c data 2ma i/o table 2. pin description (continued) pin pin name pin description/note pin drive pin type
stlc1502 10/72 pcm i/f 104 pdx pcm downstream data i 105 pdr pcm upstream data 2ma o 106 pfs pcm input/output frame synchronization 2ma i/o 107 pdc pcm input/output data clock 4ma i/o spi i/f 109 sck spi interface clock 2ma o 110 smi spi master data input i 111 smo spi master data output 2ma o kbd/gpio/hpi i/f 9 gpio0_r1_hpidata0 gpio[0] or keypad matrix row 1 or hpidata[0] 4ma i/o 10 gpio1_r2_hpidata1 gpio[1] or keypad matrix row 2 or hpidata[1] 4ma i/o 11 gpio2_r3_hpidata2 gpio[2] or keypad matrix row 3 or hpidata[2] 4ma i/o 14 gpio3_r4_hpidata3 gpio[3] or keypad matrix row 4 or hpidata[3] 4ma i/o 15 gpio4_r5_hpidata4 gpio[4] or keypad matrix row 5 or hpidata[4] 4ma i/o 16 gpio5_r6_hpidata5 gpio[5] or keypad matrix row 6 or hpidata[5] 4ma i/o 17 gpio6_c1_hpidata6 gpio[6] or keypad matrix col 1 or hpidata[6] 2ma i/o 18 gpio7_c2_hpidata7 gpio[7] or keypad matrix col 2 or hpidata[7] 2ma i/o 19 gpio8_c3_hpiadr0 gpio[8] or keypad matrix col 3 or hpiadr[0] 2ma i/o 20 gpio9_c4_hpiadr1 gpio[9] or keypad matrix col 4 or hpiadr[1] 2ma i/o 23 gpio10_c5_hpiadr2 gpio[10] or keypad matrix col 5 or hpiadr[2] 2ma i/o 24 gpio11_c6_hpiclk gpio[11] or keypad matrix col 6 or hpiclk input 2ma i/o 25 gpio12_dreq gpio[12] or dma input request (software selection) 2ma i/o 26 gpio13_dack gpio[13] or dma output acknowledge (software selection) 2ma i/o 27 gpio14_hpics_d950idle gpio[14] or hpi chip select (active low) or d950 emulator output idle state 2ma i/o 28 gpio15_hpias_d950snap gpio[15] or hpi address strobe (active low) or d950 snap output sate 2ma i/o table 2. pin description (continued) pin pin name pin description/note pin drive pin type
11/72 stlc1502 29 gpio16_hpirw_treqb gpio[16] or hpi read (active high) write (active low) strobe or tic request b input. the tic mode is forced selecting the proper test configuration through testsel[3..0] pin 2ma i/o 30 gpio17_hpiint_tack gpio[17] or hpi interrupt out or tic acknowledge output. the tic mode is forced selecting the proper test configuration through testsel[3..0] pin 2ma i/o 33 gpio18_irq1 gpio[18] and external interrupt input 1 2ma i/o 34 gpio19_irq2 gpio[19] and external interrupt input 2 2ma i/o test signal 55, 56, 57, 58 testsel[0..3] test mode selection i stradivarius stlc1502 and/or arm?s jtag 119 tdi data input i 120 tdo data output 2ma o 121 tms test mode select i 122 tck clock i 123 trstn jtag input reset i d950?s jtag 35 d950tdi data input i 36 d950tdo data output 2ma o 37 d950tms tms command i 38 d950tck clock i 39 d950trstn reset input i d950?s emu signals 54 d950erqn halt request to enter emulation mode i power and ground pins 1, 12, 21, 31, 67, 76, 83, 90, 97, 124, 132, 139, 147, 164, 180, 192, 199 vdd3 i/o power p 7, 13, 22, 32, 40, 51, 60, 68, 80, 87, 94, 101, 108, 115, 128, 143, 151, 157, 163, 173, 179, 191 gnd core ground p 8, 48, 59, 114, 172, 187 vdd core power p 49 pll_vss pll digital ground p 50 pll_vdd pll analog power supply 2.5v p table 2. pin description (continued) pin pin name pin description/note pin drive pin type
stlc1502 12/72 7 arm memory configuration the amba bus system allows to ha ndle memory blocks and peripherals on distinct buses, in order to optimize the ahb architecture for maximum speed. the memory blocks are attac hed to the ahb bus so arm c ode can run at maximum speed. an internal rom is used to store boot code that polls serial peripherals (i2c eeprom, uart) and hpi for code download in external ram. after download, the control is given to code in external ram. an internal ram is used to store arm7 interrupt vectors and some data (network frames) four external memory types can be connected. flash sram dram (sdram or edo) serial eeprom flash, sram, dram share the same 32 bits data bus and 32 bits address bus. little/big endian mode is software programmable for the dram memory controller. serial eeprom can be con- nected to the i2c bus. the chip provides the option of booting from flash or from serial eeprom, by selection from an external boot_sel pin. so different memory configurations are possible depending on the applica- tion: 1. flash, dram: the boot code including bootp and tftp is stored in flash. application can be stored in flash also, or can be downloaded into dram from ethernet network or uart. 2. eeprom, dram: the boot is performed from internal rom. the rom code loads the c ode stored in eprom that includes bootp and tftp. ap plication code will be dow nloaded into dram from ethernet or uart. 3. flash, dram, eeprom: it is like case 1, but has more flexibility. the eeprom can be used to store network parameter data (mac address) and other specif ic board data, so the code to store in flash is the same for all the platforms, and you do not need to split the flash in a permanent storage area and in an upgradable storage area. the eeprom can also be used to allow the programming of the flash the first time with a code downloaded from ethernet network. 4. dram: the boot is performed from internal rom. the application code is downloaded from the host processor through the hpi (*) interface. to access external memory bus an internal decoder is imple- mented, that can select different external memory devices. 32 bits data bus is provided with the pos- sibility to select external access es at 16 and 8 bits for each memory bank. for example the flash can be at 16 bits and the dram at 32 bits. there are 3 chip select available for static memory (4mbytes each), 4 chip selects for dynamic memory (8mbytes each). (*) note: hpi interface is available only on request 7.1 arm memory map the arm microprocessor sees 5 main memory areas. actually the memory map depends on the phase the microprocessor is working on: boot from internal rom phase (remap=0 and boot_sel=0); boot from external flash phase (remap=0 and boot_sel=1); operating phase (remap=1). the first two phases are alternative (only one of them happens at the power on reset, while the third happens after the boot.
13/72 stlc1502 8 ahb bus ahb bus is a 32 bits data and 32 bits address bus. 8.1 internal ram an internal static ram 2048x 32 is mapped starting at address 0x0 in operational mode and is used for arm interrupt vector tables. 8.2 esm interface the esm (external static memory) interface is used to access static rams or flash devices. it pro- vides 3 chip select signals and gives external access to 21 address bits, so that the memory space accessible through each chip select is 4 mbytes. the data bus on esm external interface is 32bits wide, with the additional ability to perform 16 and 8 bits accesses. little endian byte ordering is used. the data bus and address bus pins are shared with the dram driver, using ebi interface. programmable per chip-select wait-states from 0 to 15 internal clock cycles are available. at reset, every cs space has 15 wait states. the actual value is contained in the downloaded code. the external memory spaces are mapped by the esm interface as reported in figure 4. there are 3 addressable memory spaces 0x00400000 byte long each. figure 4. esm memory map following is the list of the available external signals that implement sram or flash read and write cycles. data and address buses are not shown as they are shared with the dram ebi interface. table 3. name signal type description esm_cs (2:0) out chip select. asserted when the esm decodes the proper address space in order to select the right external device external esm 04000000 esm_cs1 esm_cs0 esm_cs2 reserved 04000000 043fffff 047fffff 04800000 04bfffff 07ffffff 07ffffff 04400000 04c00000 memories
stlc1502 14/72 a scheme of the esm control interface is reported in figure 5. figure 5. esm control interface every cs space can be programmed through internal register (one for each cs) in order to: select the number of wait states to perform external access depending on the speed of the external device mapped on that memory area select if the data bus is x8 or x16 (available only for cs1 to cs2). when the x8 memories are used, their data bus has to be placed on the esm_d(7:0) signals the wait states number for the external memories (depending on memory access time) is obtained from the software code during the download phase. during the initialization phase, it is the responsibility of the software to determine if a sram or a flash is present or not on a given cs space and the width of cs1-2 memories (if present). it is possible to connect every csx to a dual port sram and use that as a communication mailbox between the device and an external microprocessor. for example, the microprocessor can write a message in the memory using one port and can send an interrupt to the device so that the execution routine related with that interrupt can read from the other port of the memory connected to the same csx of the esm. viceversa, the esm can write a message in the memory and then can send an interrupt to the external micro- processor that will r ead the message from the other port of the memory. the sram and the flash devices that are used as references are standard. oe out output enable. asserted during a read cycle (shared with edm) we[3:0] out bytes write enable. they are used to select one/two bytes when a x16/x32 flash/sram is present (shared with edm). 0: lower byte 1: 2nd byte 2: 3rd byte 3: higher byte esm_cs0width in this input informs whether a x8 (esm_cs0width=0) or x16 (esm_cs0width=1) device is present on the cs0. this information is needed the boot from external memory is selected. a[21:0] out 22 address lines for up to 4mbytes address space (shared with edm a[13:0]) d[31:0] inout data bus(shared with edm bus) name signal type description esm_cs (2:0) oe we[3:0] external side device side esm_cs0width
15/72 stlc1502 esm address decoding scheme the esm block includes also a decoder in order to generate the proper cs to the external device. in particular this decoder w ill work on the bit 22,23,24 and 25 of the internal arm address bus. esm decoding scheme 8.2.1 esm register map [ 0x0c600000 ] the base address of the esm register is 0x0c600000. 8.3 edm interface the edm interface is used to access external drams. this block supports both edo and sdram interfaces with enough flexib ility to be used with several dram chips available in the market. this block has a s eparate bus for control (the registers are placed on the apb bus) and for data (data and address are placed on the asb bus) and also includes an external bus interface that allows to share address and data bus pins with the static esm interface. figure 6 shows a block diagram of the edm block. esm decoder esm_a(21:0) address register name r/w notes esmbase + 0x00 cs0 r/w cs0 bank control esmbase + 0x04 cs1 r/w cs1 bank control esmbase + 0x08 cs2 r/w cs2 bank control
stlc1502 16/72 figure 6. edm block diagram it is possible to connect up to 4 external chips with x8, x16, and x32 data bus. each memory bank space is 8mbytes big so that a standard 64mbit dram device can be connected. it is not possible to use a single 32mbytes memory device. it is the responsib ility of the arm code to pr operly configure the edm block to initialize the dram at startup. the external memory is mapped by the edm interface as shown in fig. 7. refresh esm registers ahb interface external static data mux external bus interface ahb bus apb bus contro l addres s data memory driver memory controller tic
17/72 stlc1502 figure 7. edm memory map in the following table there is the list of the available external signals of the edm interface. table 4. the edm block includes a decoder in order to generate proper cs to the external device. in particular this de- name signal type description edm_cs(3:0) out chip select. asserted when the edm decodes the proper address space in order to select the right external device. to be connected to ras signal in case of use of edo memories edm_clk out sdram memory clock (same as arm clock). not used with edo. edm_clken out sdram clock enable. not used with edo. edm_ras out sdram ras signal. not used with edo. edm_cas out sdram cas signal. not used with edo oen out sram output enable. not used with sdram edm_we out dram write enable edm_bs(3:0) out sdram byte strobe. cas when edo memories are used edm_a(21::0) out dram address lines, only 14 lines are driven.. lines.21:14 are driven by static memory controller edm_d(31:0) inout dram data lines, shared with static memory controller lines. external edm 11800000 edm_cs0 edm_cs1 edm_cs2 edm_cs3 13ffffff 117fffff 11000000 10ffffff 10800000 107fffff 10000000 reserved 11ffffff 12000000 10000000 13ffffff dram
stlc1502 18/72 coder will work on bits 25 and 26 of internal arm address bus. edm decoding scheme every cs space can be programmed through internal register in order to configure the edm to work with the proper external device the dram controller has nine registers, the config uration register, four bank registers and four sdram configuration registers. the registers are accesses via the apb bus. the register data path is 16 bits wide. 8.3.1 edm register map [0x0c580000] the base address of the edm register is 0x0c580000 table 5. edm decoder edm_a(13:0) address register name r/w notes edmbase + 0x00 mb1config r/w memory bank 1 configuration register edmbase + 0x04 mb2config r/w memory bank 2 configuration register edmbase + 0x08 mb3config r/w memory bank 3 configuration register edmbase + 0x0c mb4config r/w memory bank 4 configuration register edmbase + 0x10 sdram1configl o wo memory bank 1 low sdram configuration register edmbase + 0x14 sdram1configh i wo memory bank 1 high sdram configuration register edmbase + 0x18 sdram2configl o wo memory bank 2 low sdram configuration register edmbase + 0x1c sdram2configh i wo memory bank 2 high sdram configuration register edmbase + 0x20 sdram3configl o wo memory bank 3 low sdram configuration register edmbase + 0x24 sdram3configh i wo memory bank 3 high sdram configuration register edmbase + 0x28 sdram4configl o wo memory bank 4low sdram configuration register edmbase + 0x2c sdram4configh i wo memory bank 4 high sdram configuration register edmbase + 0x30 memconfig r/w memory configuration register
19/72 stlc1502 memory bank configuration registers memory bank configuration registers are used to setup memory bank specific parameters: devwid: device width defines the data width of the external memory device: 00 - byte (8 bit) 01 - half word (16 bit) 10 - word (32 bit) datalat: data latency defines the number of memory clock cycles between the start of a memory read access and the first valid data. the datalat value is valid between 0 and 3. setuptime: setup time defines the number of memory clock cycles the me mory driver spends in the decode state before accessing the external memory. the setuptime value is valid between 0 and 7. idletime: idle time defines the minimum time the memory driver must spend in the idle state following memory accesses. the value defines the number of memory clock cycles. the idletime value is valid between 0 and 7. sdramcol: sdram column width definition specifies the width of the sdram column address: 00 - 8 bits 01 - 9 bits 10 - 10 bits 11 - reserved sdram configuration registers these registers are write only. a write access to the high registers will start the sdram configuration cycle, during which the value written to the register will be asserted on the memory bus for a one clock period. low sdram configuration registers 1514131211109876543210 reserved devwid datalat setup time idletime sdramc ol 1514131211109876543210 reserved miab
stlc1502 20/72 miab: memory interface address bus high sdram configuration registers miab: memory interface address bus miwe: memory interface write enable miaa: memory interface access active (ncas) misa: memory interface setup active (nras) after the power-up the cpu must configure each sdram device, i.e. perform precharge-refresh-mode register set procedure. memory configuration register memory configuration registers are used to setup parameters that are same for all banks: pws: power save mode if pws bit is set to?1?, the next refresh cycle will set the memory devices in the self-refresh mode. the memories will exit the self-refresh mode, when the pws mode is set to?0?. type: memory type: the type bit is used to select a type of the external memory. 1 - sdram 0 - edo b3en: bank 3 enable b2en: bank 2 enable b1en: bank 1 enable b0en: bank 0 enable the bank enable bits are used to enable each bank separately. if an ahb transfer is accessing a disabled bank, the dram controller will return the error response to the ahb master. refr: refresh period the refr value is used to determine the refresh period. the period can be set in the 1 us steps. refr refresh period 00000000 refresh is disabled 00000001 refresh period is 1us 00000010 refresh period is 2us. 11111111 refresh period is 255us 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved mive miaa misa 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved pws type b3en b2en b1en b0en refr
21/72 stlc1502 8.4 dma controller the dma controller is intended to be used with the ethernet switch block to transfer ethernet frames between the ethernet switch buffers and memory. the dma needs initialization before starting operation. during operation it does not need intervention from the arm controller. in receive, when the complete frame is stored in memory, the dma asserts the interrupt for the arm that can read the frame. in transmit the dma provides an interrupt when the complete frame is transferred. 8.5 ethernet dma-macs the ethernet block includes two identical mac cores that can operate in half-duplex and full-duplex modes. when operating in half-duplex mode, the mac cores are fully compliant to section 4 of iso/iec 8802-3 (ansi/ieee standard) and ansi/ieee 802.3. when operating in full-duplex mode, the mac cores are fully compliant to ieee 802.3x standard for full-duplex operations. they are also compatible with homepna 1.1. main features of the block are: internal fifos for easy dma transfers. full duplex support using separate tx, rx fifos. vlan support 10/100 mb/s data transfer rates the mac cores provide 2 mii interfaces to connect two external phys. 8.5.1 the dma descriptors chain the descriptor list is the mean the cpu and the dma_mac use to communicate each other in order to transmit/ receive frames on the cable. this list must be properly prepared before initiating any transfer activity to/from the cable. the descriptor is produced by the cpu and consumed by the dma_mac. figure 8. a descriptor is a 16-bytes element which provides the dma_mac with information about how to transmit/receive a single frame and how to report the transfer status back to the cpu. dma_cntl dma_addr dma_next tx/rx_status dma_cntl dma_addr dma_next tx/rx_status dma_cntl dma_addr dma_next tx/rx_status frame 0 frame 1 frame n ... descr 1 descr 2 descr n (4 x 4 bytes) (4 x 4 bytes) (4 x 4 bytes)
stlc1502 22/72 a descriptor can be stored in any main memory location with a 32-bit aligned address. the first 3 words stored in a descriptor are expected to be the values of the 3 dma_mac registers describing a dma transfer (dma_cntl, dma_addr and dma_next). when the dma_mac fetches a descriptor it loads this three values into its own corresponding registers. the last word is to be used by the dma_mac to report the transfer status. 8.5.2 the descriptor control bits the descriptor keeps information about a single frame transfer and how to access the next descriptor. the following discussion is related to 3 bits of the descriptor: the valid bit, the nxt_en bit and the npol_en bit. the descriptor can be accessed simultaneously by the cpu and the dma_mac. this concurrent access is synchronized by the valid bit in the dma_cntl register. when the valid bit is equal to 0 then the cpu is the owner of the descriptor. otherwise the owner is the dma_mac. since the descriptor can be ac- cessed in write mode by the owner only at any time, race conditions are guaranteed to never happen. the nxt_en bit enables the fetch of the next descriptor. when the dma_mac finds this bit set to 0 then its activity is considered to be completed as soon as the current descriptor dma transfers have been com- pleted. the npol_en bit enables the dma_mac to keep polling for a non-valid descriptor until its valid bit is set to one. when the dma_mac finds both the npol_en bit and the valid bit set to 0 then its activity is considered to be completed. 8.5.3 transfer interrupts the dma_mac can interrupt the cpu with three different levels of information about transfer completion. the cpu can choose which interrupt needs to be enabled. they do not exclude each other though; they can be all three enabled at the same time. the tx_curr_done (rx_curr_done) interrupt bit reports the cpu when a single descriptor (i.e. one frame) has been completely treated by the dma_mac and the cpu is again the owner (valid bit set to 0). the tx_next (rx_next) interrupt bit is set when next descriptor fetch is enabled (nxt_en=1 in the current descriptor) the next descriptor is not valid (valid bit is off). the tx_done (rx_done) interrupt bit is set when a whole dma transfer is complete. this can happen either when the current is the last descriptor in the chain (nxt_en is off) or when the next descriptor is not valid yet (valid bit is off) and the polling is disabled (npol_en bit is off). 8.5.4 frames transmission (tx) when the cpu wants to transmit a set of frames on the cable, it needs to provide the dma_mac with a descriptor list. the cpu is expected to allocate a descriptor for each frame it wants to send, to fill it with the dma control information and the pointer to the frame, and to link the descriptor in the chain. the frames will be s ent on the cable in the same order they are found in the chain. 8.5.5 open list approach the simplest way to construct a descriptor chain is the open list approach. every descriptor but the last one will have the dma_next field pointing to the next descriptor in the chain, the nxt_en bit and the val-
23/72 stlc1502 id bit on, the npol_en bit on/off. the last descriptor will be set in the same way except for the nxt_en bit (off) and the dma_next field (null). the cpu starts the dma activity loading the physical location of the first descriptor into the dma next register of the dma_mac and set the dma start register enable bit to on. the dma_mac will then keep fetching the descriptors one by one until it finds the nxt_en bit of the last descriptor set to off. every time it completes a descriptor (frame) it saves the transfer status into txrx_status, it turns the descriptor valid bit to off and raises the tx_curr_done interrupt bit. when the nxt_en bit is found to be off, that means the dma_mac has fetched the last descriptor in the chain. when it completes also this descriptor (the end of the dma transfer) it raises both the tx_curr_done and the tx_done interrupt bits. 8.5.6 closed list approach the approach above is easy since it doesn?t require the dma_mac and the cpu to synchronize their ac- cess to the descriptor chain. the problem is that it requires the cpu to build the list every time it needs a transfer. a faster way to operate is building a closed descriptor list only the first time and using the valid bit to mark the end of the transfer. the polling facility could also be used to save the cpu from the activity of programming the dma start register every time it needs to start the dma transfer. instead, the dma start register will be activated only once and the dma_mac will keep polling the invalid descriptor, raising each time the tx_next interrupt bit (if enabled), until the cpu finally sets its valid bit to on. since the dma transfer practically never ends, note that in this case the tx_done interrupt bit is never raised. with this approach every descriptor will have the dma_next field pointing to the next descriptor in the chain (the last one will point to the first one), the nxt_en bit, the valid bit and the npol_en bit on. the dma_mac will keep fetching the descriptors one by one until it finds one with its valid bit set to off. every time the dma_mac completes a descriptor (frame) it saves the transfer status into txrx_status, it turns its valid bit to off and ra ises the tx_curr_done interrupt bit. 8.5.7 frames reception (rx) the frame reception process is something that needs to be activated at the beginning and kept always running. for this reason the closed descriptor list (see above) is much more useful than the open list ap- proach. again, with this approach every descriptor will have the dma_next field pointing to the next descriptor in the chain (the last one will point to the first one), the nxt_en bit, the valid bit and the npol_en bit on. the cpu starts the transfer activity loading the dma next register of the dma_mac with the physical lo- cation of the first descriptor and set the dma start register enable bit to on.the dma_mac will start fetch- ing the descriptors one by one, driven by the frames reception from the line. every time the dma_mac completes a descriptor (frame) it saves the transfer status into txrx_status, it turns its valid bit to off and raises the tx_curr_done interrupt bit. eventually, the dma_mac will be faster than the cpu, it will wrap around the de scriptor chain and find a descriptor still invalid. then the dma_cnt keeps polling the invalid descriptor, raising each time the tx_next interrupt bit (if enabled), until some descriptor gets available (note that in this case some frame could be lost). in the
stlc1502 24/72 meantime the cpu should consume the frames received and set the valid bit to on of all the descriptor released. as soon as the dma_cnt finds the descriptor valid again, it will be able to complete the transfer and to fetch the next descriptor. 8.5.8 ethernet block register map [0x0c680000] the base address of the ethernet registers is 0x0c680000 the memory map of the dual mac ethernet block is shown below: table 6. address register name notes dma_mac1 eth_base1=0x0c680000 eth_base1+ 0x0000 dma_st&cntl dma status and control register eth_base1+0004 dma_int_en dma interrupt sources enable register eth_base1+0008 dma_int_stat dma interrupt status register eth_base1+000c reserved eth_base1+ 0x0010 rx_dma_start rx dma start register eth_base1+ 0x0014 rxd_dma_cntl rx data dma control register eth_base1+ 0x0018 rxd_dma_addr rx data dma base address register eth_base1+ 0x001c rxd_dma_nxt rx data dma next descriptor address register eth_base1+ 0x0020 rx_dma_caddr rx dma current address register eth_base1+ 0x0024 rx_dma_cxfer rx dma current transfer count register eth_base1+ 0x0028 rx_dma_to rx dma fifo time out register eth_base1+ 0x002c rx_dma fifo rx dma fifo status register eth_base1+ 0x0030 rxv_dma_cntl rx voice dma control register eth_base1+ 0x0034 rxv_dma_addr rx voice dma base address register eth_base1+ 0x0038 rxv_dma_nxt rx voice dma next descriptor address register eth_base1+0x003c- eth_base1+0x 004c reserved eth_base1+ 0x0050 tx_dma_start tx dma start register eth_base1+ 0x0054 txd_dma_cntl tx data dma control register eth_base1+ 0x0058 txd_dma_addr tx data dma base address register
25/72 stlc1502 eth_base1+ 0x005c txd_dma_nxt tx data dma next descriptor address register eth_base1+ 0x0060 tx_dma_caddr tx dma current address register eth_base1+ 0x0064 tx_dma_cxfer tx dma current transfer count register eth_base1+ 0x0068 tx_dma_to tx dma fifo time out register eth_base1+ 0x006c tx_dma fifo tx dma fifo status register eth_base1+ 0x0070 txv_dma_cntl tx voice dma control register eth_base1+ 0x0074 txv_dma_addr tx voice dma base address register eth_base1+ 0x0078 txv_dma_nxt tx voice dma next descriptor address register eth_base1+0x007c- eth_base1+ 0x00fc reserved eth_base1+ 0x0100 rx_fifo_0 rx fifo 32 bit word #0 .... ... ... eth_base1+ 0x013c rx_fifo_15 rx fifo 32 bit word #15 eth_base1+ 0x0180- eth_base1+ 0x01fc reserved eth_base1+ 0x0200 tx_fifo_0 tx fifo 32 bit word #0 .... ... ... eth_base1+ 0x023c tx_fifo_15 tx fifo 32 bit word #15 eth_base1+ 0x0280- eth_base1+ 0x03ff reserved eth_base+ 0x0400- eth_base+ 0x07ff mac110 dma_mac2 eth_base2 = 0x0c680800 eth_base2+ 0x000 dma_st&cntl dma status and control register eth_base2+0x0004 dma_int_en dma interrupt sources enable register eth_base2+0x8008 dma_int_stat dma interrupt status register eth_base2+0x000c reserved eth_base2+ 0x0010 rx_dma_start rx dma start register eth_base2+ 0x0014 rxd_dma_cntl rx data dma control register address register name notes
stlc1502 26/72 eth_base2+ 0x0018 rxd_dma_addr rx data dma base address register eth_base2+ 0x001c rxd_dma_nxt rx data dma next descriptor address register eth_base2+ 0x0020 rx_dma_caddr rx dma current address register eth_base2+ 0x0024 rx_dma_cxfer rx dma current transfer count register eth_base2+ 0x0028 rx_dma_to rx dma fifo time out register eth_base2+ 0x002c rx_dma fifo rx dma fifo status register eth_base2+ 0x0030 rxv_dma_cntl rx voice dma control register eth_base2+ 0x0034 rxv_dma_addr rx voice dma base address register eth_base2+ 0x0038 rxv_dma_nxt rx voice dma next descriptor address register eth_base2+0x003c- eth_base2+004c reserved eth_base2+ 0x0050 tx_dma_start tx dma start register eth_base2+ 0x0054 txd_dma_cntl tx data dma control register eth_base2+ 0x0058 txd_dma_addr tx data dma base address register eth_base2+ 0x005c txd_dma_nxt tx data dma next descriptor address register eth_base2+ 0x0060 tx_dma_caddr tx dma current address register eth_base2+ 0x0064 tx_dma_cxfer tx dma current transfer count register eth_base2+ 0x0068 tx_dma_to tx dma fifo time out register eth_base2+ 0x006c tx_dma fifo tx dma fifo status register eth_base2+ 0x0070 txv_dma_cntl tx voice dma control register eth_base2+ 0x0074 txv_dma_addr tx voice dma base address register eth_base2+ 0x0078 txv_dma_nxt tx voice dma next descriptor address register eth_base2+0x007c- eth_base2+ 0x00fc reserved eth_base2+ 0x0100 rx_fifo_0 rx fifo 32 bit word #0 .... ... ... eth_base2+ 0x013c rx_fifo_15 rx fifo 32 bit word #15 address register name notes
27/72 stlc1502 8.6 arbiter the arbiter is used to ensure that, at any point in time, only one master has access to the bus. it performs this function by observing all of the bus master requests to use the bus, and deciding which is currently the highest priority. it has a standard interface to all bus masters and split-capable sl aves in the system. however it does not support split bus transfers. a bus master may request the bus dur ing any cycle by setting its hbusreq output high. this is then sampled by the arbiter on the rising edge of the clock, and passed through the priority algorithm to decide which master will have access to the bus during the next cycle. the hgrant then outputs change to indicate which master currently is granted control of the bus. the hlock signals may be used to ensure that during an indivisible transfer, the current grant outputs do not change. hlock must be asserted at least one cycle before the locked transfer to prevent the arbiter from changing the grant signals. when more than one master requests ownership of the system bus, the priority used for arbitration is: highest: tic printer drive control dma controller lowest: arm7tdmi (default master) the arm7tdmi will periodically assume top priority on the system bus: this period can be programmed. also, it will assume top priority when an interrupt occurs, if the interrupt mode is enabled. during reset, and when no other masters are requesting control of the bus, the arm7tdmi is selected as the currently granted master. this minimizes the delay required for the core to perform a transfer on the bus, as it does not have to wait to be granted control of the bus before it can start a new transfer. the system also requires a default master, which is se lected when no masters are granted control of the bus, for example, when all system bus masters are waiting for split transfers to complete. the default master per- forms idle transfers while it is granted control of the bus. the bus grant outputs may change while hready is low, but the newly granted master may only drive the bus when the current transfer has completed. this requires that bus masters only drive the bus after they detect that both their hgrant and hready inputs are set high. all registers used in the system are clocked from the rising edge of the system clock hclk, and use the asyn- chronous reset hresetn. the arbiter control and status registers are accessed via the apb bus. eth_base2+ 0x0180- eth_base2+ 0x01fc reserved eth_base2+ 0x0200 tx_fifo_0 tx fifo 32 bit word #0 .... ... ... eth_base2+ 0x023c tx_fifo_15 tx fifo 32 bit word #15 eth_base2+ 0x0280- eth_base2+ 0x03ff reserved eth_base2+ 0x0400- eth_base2+ 0x07ff mac110 refer to the insilicon mac110 specification (see ref. [2]) address register name notes
stlc1502 28/72 8.7 tic-test interface controller the test interface controller (tic) is a state machine that provides an amba ahb bus master for system test. it reads test write and address data from the external data bus testbus (xd), and uses the external bus in- terface (part of the dram controller) to drive the external bus with test read data, allowing the use of only one set of output tristate buffers onto testbus. the tic is used to convert externally applied test vectors into internal transfers on the ahb bus. a three-wire external handshake protocol is used, with two inputs controlling the type of vector that is applied and a single output that indicates when the next vector can be applied. typically the tic is the highest priority amba bus master, which ensures test access under all conditions. the tic model supports address incrementing and con- trol vectors. this means that the address for burst transfers can automatically be generated by the tic. 8.8 ahb-asb bridge the apb bridge is the only bus master on the advanced peripheral bus. in fact, the apb bridge is also a slave on the ahb. the bridge unit converts asb transfers into apb transfers. on the apb bus only 16 bits wide data accesses are permitted. 32 bit wide and 8 bit wide transfers are not supported. all the apb peripherals decodes all the 16 bits of the pa bus. apb decoding scheme every area is 128k x 16 bits but the area actually available is 32k x 16 due to the fact that the address lines on the apb bus are 16 (pa(15:0)). that means that in every area dedicated to the several block on the apb bus only the first ffff is usable. 9 apb bus the apb bus is a 16 bits data and 16 bits address bus. the blocks attached on this bus are described in the following sections while the memory area is reported in the following figure. all the addresses in the apb space are word aligned (addresses are multiples of four) apb decoder space pa(15:0)
29/72 stlc1502 figure 9. apb memory map spi port reserved interrupt controller dual port sram ethernet mac dmacs 0c000000 0c07ffff 0c6fffff 0c4fffff 0c100000 0c17ffff 0c080000 0cofffff 0c180000 0c1fffff 0c200000 0c27ffff 0c3fffff 0c280000 0c400000 0c47ffff 0c480000 i2c port 0c300000 edm regs gpio esm regs 0c600000 0c5fffff 0c580000 0c500000 watchdog timer 0c67ffff 0c680000 0c800000 uart hpi 0c2fffff 0c37ffff 0c380000 timer miscellaneous i/o dmac 0c57ffff 0c8fffff 0c700000 0c7fffff arm/d950 bridge
stlc1502 30/72 9.1 timer the timer module connects to the advanced peripheral bus. figure 10. timer block diagram this implementation consists of two major sections comprising: all the control logic two instantiations of the free-running counters (frcs) the timer module has a series of memory-mapped locations that allow the state of the timer module to be read from and written to via the apb. 9.1.1 timer introduction two timers are defined and can be selected by the control register: free-running mode:the timer wraps after reaching its zero value, and continues to count down from the maximum value. periodic timer mode:the counter generates an interrupt at a constant interval. 9.1.2 timer operation the timer is loaded by writing to the load register and, if enabled, counts down to zero. when zero is reached, an interrupt is generated. the interrupt may be cleared by writing to the clear register. after reaching a zero count, if the timer is operating in free-running mode it continues to decrement from its max- imum value. if periodic timer mode is selected, the timer reloads from the load register and continues to decre- ment. in this mode the timer effectively generates a periodic interrupt. the mode is selected by a bit in the control register. at any point, the current timer value may be read from the value register. cktimer pwdata [15:0] pa[15:0] pwrite penable bnres dsel_timer intct1 intct2 prescaler load registers control registers control logic control section frc - free running counter frc - free running counter timer section prdata [15:0] intct3 intct4 to pic to edm
31/72 stlc1502 the timer is enabled by a bit in the control register. at reset, the timer is disabled, the interrupt is cleared and the load register is undefined. the mode and prescale values are also undefined. figure 11. timer block diagram the timer clock is generated by a prescale unit. the timer clock may be one of: the cktimer the cktimer divided by 16, generated by 4 bits of prescale the cktimer divided by 256, generated by a total of 8 bits of prescale figure 12. pre-scaler block diagram using the recommended 2.208mhz clock, the minimum interval between two timer interrupt is 452nsec (corre- sponding to the 2.208mhz period) while the maximum interval between two timer interrupt is around 6sec. terminal count interrupt value load control timer clock 16-bit down counter load register control register divide by 16 cktimer pre-scale unit prescale select divide by 16 timer clock
stlc1502 32/72 9.1.3 timer register map [0x0c000000] the base address of the timer register is 0x0c000000 the offset of any particular register from the base address is the following. table 7. address register name r/w notes timerbase + 0x00 timer1load r/w timer1load . the load register contains the initial value of the timer and is also used as the reload value in periodic timer mode. timerbase + 0x04 timer1value r timer1value . the value location gives the current value of the timer. timerbase + 0x08 timer1control r/w timer1control . the control register provides enable/disable, mode and prescale configurations for the timer (see figure 10). timerbase + 0x0c timer1clear w timer1clear. writing to the clear location clears an interrupt generated by the counter timer. timerbase + 0x10 timer2load r/w timer2load . the load register contains the initial value of the timer and is also used as the reload value in periodic timer mode. timerbase + 0x14 timer2value r timer2value . the value location gives the current value of the timer. timerbase + 0x18 timer2control r/w timer2control . the control register provides enable/disable, mode and prescale configurations for the timer (see figure 10). timerbase + 0x1c timer2clear w timer2clear. writing to the clear location clears an interrupt generated by the counter timer. timerbase + 0x20 timer3load r/w timer3load . the load register contains the initial value of the timer and is also used as the reload value in periodic timer mode. timerbase + 0x24 timer3value r timer3value . the value location gives the current value of the timer. timerbase + 0x28 timer3control r/w timer3control . the control register provides enable/disable, mode and prescale configurations for the timer (see figure 10). timerbase + 0x0c timer3clear w timer3clear. writing to the clear location clears an interrupt generated by the counter timer. timerbase + 0x30 timer4load r/w timer4load . the load register contains the initial value of the timer and is also used as the reload value in periodic timer mode. timerbase + 0x34 timer4value r timer4value . the value location gives the current value of the timer. timerbase + 0x38 timer4control r/w timer4control . the control register provides enable/disable, mode and prescale configurations for the timer (see figure 10). timerbase + 0x3c timer4clear w timer4clear. writing to the clear location clears an interrupt generated by the counter timer.
33/72 stlc1502 9.2 watchdog timer stlc1502 contains a watchdog timer. this timer is used to reset the arm7 in case of a software deadlock. the watchdog timer generates a hot reset when it overflows which will restart the arm, but the code will not be downloaded again. the timer should be cleared by the software before it overflows. it is based on a 8 bit counter which is clocked by a slow signal coming from a 17 bit prescaler clocked by the system clock. so the elapsing time of the watc hdog timer depend on the system clock: sys_clk: 13mhz => 2.58 seconds 26mhz => 1.29 seconds 39mhz => 0.86 seconds 52mhz => 0.64 seconds this peripheral consists of a timer that continue to run and to reset the core if the software doesn? t clear it before it elapses. the software can clear or disable the timer by writing the wdog_control register 9.2.1 watch dog register map [0x0c500000] the base address of the wdt register is 0x0c500000 the memory map of the wdt peripheral is shown below: table 8. 9.3 miscellaneous i/o all the registers not related to any module attached to the apb/ahb bus su ch as eii, test are considered mis- cellaneous i/o. additionally, the esm configuration register and the dual port register are also part of this block. 9.3.1 miscellaneous register map [0x0c080000] the miscellaneous register address is 0x0c080000 table 9. address register name r/w notes esmbase + 0x00 wdtcontrol r/w wdt control register esmbase + 0x04 wdt reset_stat r/w wdt reset the status register esmbase + 0x08 wdt max_count r/w wdt programmable max count esmbase + 0x0c wdt counter r wdt internal counter value address register name r/w notes misc_regbase+ 0x00 control w this register allows to control the reset/boot procedure and some other control features misc_regbase+ 0x04 status w this register allows dsp section setting misc_regbase+ 0x08 identification r this register provides informations about the device/system
stlc1502 34/72 9.4 interrupt controller in an arm system, two levels of interrupt are available: fiq (fast interrupt request) for fast, low latency interrupt handling irq (interrupt request) for more general interrupts ideally, in an arm system, only a single fiq source would be in use at any particular time. this provides a true low-latency interrupt, because a single source ensures that the interrupt service routine may be executed direct- ly without the need to determine the source of the interrupt. it also reduces the interrupt latency because the extra banked registers, which are available for fiq interrupts, may be used to maximum efficiency by preventing the need for a context save. separate interrupt controllers are used for fiq and irq. there are 15 interrupt causes available in the irq controller coming from: software (internally generated) timer1 timer2 uart dual port ram i2c ethernet switch dmac1 ethernet switch dmac2 spi dmac irq1/gpio18 irq2/gpio19 ikybd hpi timer3 even if only a single bit position is defined for fiq, the interrupt controller can drive one of the interrupt source (irq interrupt sources), through a register, in order to generate the fiq interrupt. the irq interrupt controller uses a bit position for each different interrupt source. all interrupt source inputs must be active high and level sensitive and it remain active until the interrupt cause has been cancelled. no hardware priority scheme nor any form of interrupt vectoring is provided, because these functions can be provided in software. a programmed interrupt register is also provided to generate an interrupt under software control. every interrupt source can be masked. 9.4.1 interrupt control the irq interrupt management is done as described in the following: an interrupt is generated by a given device/source; this cause is readable by the irqrawstatus register; if not masked (the mask is set by irqenableset and reset by irqenableclear), this interrupt will generate a irq signal to the arm and the interrupt source will be known by a read of the irqstatus register. the arm will serve the irq reading at first in the irqstatus the active interrupt requests and will execute with a given priority the proper interrupt routine. every routine must erase (quite soon) in some way its interrupt request source. this causes also for the proper bit in the irqrawstatus regis- ter and in the irqstatus register to disappear. the same interlock is present for the fiq interrupt.
35/72 stlc1502 9.4.2 interrupt control scheme figure 13. interrupt block scheme bclk pwrite penable bnres dsel_int nfiq nirq irqsource[13:0] fiq control irq control nfiq nirq pwdata [15:0] pa[15:0] prdata [15:0]
stlc1502 36/72 figure 14. irq control block 9.4.3 interrupt register map [0x0c100000] the base address of the timer register is 0x0c100000 the offset of any particular register from the base address is the following. table 10. address register name r/w notes int.base + 0x00 irqstatus r for every irq interrupt cause, a ?1? means an active pending interrupt that has to be served by the arm int base+ 0x04 irqrawstatus r for every irq interrupt source, a ?1? means an active pending interrupt ?before? the mask (w/o considering the mask) int.base + 0x08 irqenableset r/w for every irq interrupt source, a ?0? means that even if an interrupt source is active, it has to be stopped (masked). the write operation of 1 to a given bit, enable the corresponding interrupt int.base + 0x0c irqsoft r/w only the bit 1 has to be used. writing ?1? it generates an interrupt mapped in the bit 1 of the irqstatus and of the irqrawstatus registers. writing ?0? the software interrupt cause is erased. interrupt_mask enable nirq other interrupt bit slices irqrawstatus irqstatus interrupt source interrupt pending
37/72 stlc1502 9.5 spi-serial peripheral interface the serial peripheral interface (spi) allows full-duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. the spi is normally used for communication between the microcontroller and external peripherals. int.base + 0x10 fiqstatus r for the fiq interrupt cause, ?1? means an active pending interrupt that has to be served by the arm. int base + 0x14 fiqrawstatus r for the irq interrupt source, a ?1? means an active pending interrupt ?before? the mask (w/o considering the mask) int.base + 0x18 fiqenableset r/w for the fiq interrupt source, a ?0? means that even if an interrupt source is active, it has to be stopped (masked). the write operation of 1 to the bit0, enables the interrupt int.base + 0x1c irqenableclear w the write operation of 1 to a given bit, disables the corresponding interrupt. as consequence, the corresponding bit in the irqenableset goes to 0 (interrupt disabled). int.base + 0x20 fiqenableclear w the write operation of 1 into the bit 0 disables fiq interrupt cause. as a result, the bit 0 in the fiqenableset goes to 0 (interrupt disabled). int.base + 0x24 irqtestsource r/w usable when the bit 0 of the irqsourcesel is set to one. in this case this register is the interrupt source cause. if set, the cause is active (interrupt generated) while if reset, the cause is not active. int base + 0x28 irqsourcesel r/w select the test mode of the irq cause on the interrupt controller (if the bit 0 is set). in this case the irqtestsource becomes the interrupt source cause. int.base + 0x2c fiqtestsource r/w usable when the bit 0 of the fiqsourcesel is set to one. in this case this register is the interrupt source cause. if set, the cause is active (interrupt generated) while if reset, the cause is not active. int base + 0x30 fiqsourcesel r/w select the test mode of the fiq cause on the interrupt controller (if the bit 0 is set). in this case the fiqtestsource becomes the interrupt source cause. moreover this register contains also the selection for the fiq interrupt cause. address register name r/w notes
stlc1502 38/72 9.6 main features full duplex, three-wire synchronous transfers master mode operation (clock generation) four master mode frequencies four programmable master bit rates programmable clock polarity end of transfer interrupt flag write collision flag protection master mode fault pr otection capability. the spi is connected to external devices through 3 pins: smi: master in smo: master out sck: serial clock pin when the master device transmits data to a slave device via smo pin, the slave device responds by send- ing data to the master device to the smi. this implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master device via the sck pin). thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit- empty and receiver-full bits. a status flag is used to indicate that the i/o operation is complete. the msb is transmitted first. two possible data/clock timing relationships may be chosen. 9.6.1 programming procedure the spi interface contains 3 dedicated registers: a control register (cr) a status register (sr) a data register (dr) check the register description section for bits position and functions. select the spr0 & spr1 bits to define the serial clock baud rate. select the cpol bit to define the relationship between the data transfer and the serial clock. the transmit sequence begins when a byte is written in the dr register. the data byte is parallely loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the smo pin most significant bit first. when data transfer is complete: the spif bit is set by hardware .an interrupt is generated if the spie bit is set and the i bit in the ccr register is cleared. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the dr register is read, the spi peripheral returns this buffered value. clearing the spif bit is performed by the following software sequence: 1. an access to the sr register while the spif bit is set 2. a read to the dr register. note: while the spif bit is set, all writes to the dr register are inhibited until the sr register is read.
39/72 stlc1502 9.6.2 data transfer format during an spi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in se- rially). the serial clock is used to synchronize the data transfer during a sequence of eight clock pulses. the cpol (clock polarity) bit controls the steady state value of the clock when no data is being transferred. the master device applies data to its smo pin before the capture clock edge. the first edge on the sck pin (falling edge if cpol bit is set, rising edge if cpol bit is reset) is the msbit capture strobe. data is latched on the occurrence of the first clock transition. the slave select signal is necessary in case more than one slave devices are connected on the seral bus. the slave select can be generated with a gpio pin. figure 15. 9.6.3 collision management collision is defined as a write of the dr register while the internal serial clock (sck) is in the process of transfer. the wcol bit in the sr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence: 1-read sr 2-read dr
stlc1502 40/72 9.6.4 spi register map [0x0c280000] the base address of the remap & pause register is 0x0c280000. the offset of any particular register from the base address is the following. table 11. 9.7 i2c bus interface the i2c bus interface serves as an interface between the microcontroller and the serial i2c bus. it pro- vides both multimaster and slave functions, and controls all i2c bus-specific sequencing, protocol, arbi- tration and timing. it supports fast i2c mode (400khz). 9.7.1 main features parallel-bus/i2c protocol converter multi-master capability 7-bit/10-bit addressing transmitter/receiver flag end-of-byte transmission flag transfer problem detection i2c master features: clock generation i2c bus busy flag arbitration lost flag end of byte transmission flag transmitter/receiver flag start bit detection flag start and stop generation i2c slave features: stop bit detection i2c bus busy flag detection of misplaced start or stop condition programmable i2c address detection transfer problem detection end-of-byte transmission flag transmitter/receiver flag 9.7.2 general description in addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled by software. the interface is connected to the i2c bus by a data pin (sdai) and by a clock pin (scli). it can be connected both with a standard i2c bus and a fast i2c bus. this selection is made by software. the interface can operate in the following modes: ? slave transmitter/receiver address register name r/w notes spi_regbase+ 0x04 spidr r/w spi data i/o register. spi_regbase+ 0x08 spicr r/w spi configuration register spi_regbase+ 0x0c spisr r/w spi status register
41/72 stlc1502 ? master transmitter/receiver by default, it operates in slave mode. the interface automatically switches from slave to master after it generates a start condition and from master to slave in case of arbitration loss or a stop generation, allowing then multi-master capability. in master mode, it initiates a data transfer and generates the clock signal. a serial data transfer always begins with a start condition and ends with a stop condition. both start and stop conditions are generated in master mode by software. in slave mode, the interface is capable of recognizing its own address (7 or 10 bits), and the general call address. the general call address detection may be enabled or disabled by software. data and addresses are transferred as 8-bit bytes, msb first. the first byte(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode). the address is always transmitted in master mode. a 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. figure 16. acknowledge may be enabled and disabled by software. the i 2 c interface address and/or general call address can be selected by software. the speed of the i 2 c interface may be selected between standard (0-100khz) and fast i2c (100-400khz). in transmitter mode the interface holds the clock in low before transmission to wait for the microcon- troller to write the byte in the data register. in receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the data register. the scl frequency (fscl) is controlled by a programmable clock divider which depends on the i 2 c bus mode. when the i2c cell is enabled, the sda and scl ports must be configured as floating inputs. in this case, the value of the external pull-up resistor used depends on the application.
stlc1502 42/72 9.7.3 functional description refer to the cr, sr1 and sr2 registers in register map section for the bit definitions. by default the i 2 c interface operates in slave mode (m/sl bit is cleared) except when it initiates a trans- mit or receive sequence. first the interface frequency must be configured using the fri bits in the oar2 register. 9.7.3.1 slave mode as soon as a start condition is detected, the address is received from the sda line and sent to the shift register; then it is compared with the address of the interface or the general call address (if selected by software). note: in 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and the two most significant bits of the address. header matched (10-bit mode only) : the interface generates an acknowledge pulse if the ack bit is set. address not matched: the interface ignores it and waits for another start condition. address matched: the interface generates in sequence: acknowledge pulse if the ack bit is set. evfand adsl bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 register, holding the scl line low. next, read the dr register to determine from the least significant bit (data direction bit) if the slave must enter receiver or transmitter mode. in 10-bit mode, after receiving the address sequence the slave is always in receive mode. it will enter transmit mode on receiving a repeated start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1). slave receiver after the address reception and sr1 register has been read, the slave receives bytes from the sda line into the dr register via the internal shift register. after each byte the interface generates in sequence: ? acknowledge pulse if the ack bit is set ? evf and btf bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 register followed by a read of the dr register, holding the scl line low. slave transmitter after the address reception and the sr1 register has been read, the slave sends bytes from the dr reg- ister to the sda line via the internal shift register. the slave waits for a read of the sr1 register followed by a write in the dr register, holding the scl line low. when the acknowledge pulse is received: ? the evf and btf bits are set by hardware with an interrupt if the ite bit is set. closing slave communication after the last data byte is transferred a stop condition is generated by the master. the interface detects this condition and sets: ? evf and stopf bits with an interrupt if the ite bit is set.then the interface waits for a read of the sr2 register error cases ? berr: detection of a stop or a start condition during a byte transfer. in this case, the evf and the berr bits are set with an interrupt if the ite bit is set. if it is a stop then the interface discards the data, released the lines and waits for another start condition. if it is a start then the interface discards the data and waits
43/72 stlc1502 for the next slave address on the bus. ? af: detection of a non-acknowledge bit. in this case, the evf and af bits are set with an interrupt if the ite bit is set. note : in both cases, scl line is not held low; however, sda line can remain low due to possible ?0? bits transmitted last. it is then necessary to release both lines by software. how to release the sda / scl lines: set and subsequently clear the stop bit while btf is set. the sda/scl lines are released after the transfer of the current byte. 9.7.3.2 master mode to switch from default slave mode to master mode a start condition generation is needed. start condition setting the start bit while the busy bit is cleared causes the interface to switch to master mode (m/sl bit set) and generates a start condition. once the start condition is sent: ? the evf and sb bits are set by hardware with an interrupt if the ite bit is set. then the master waits for a read of the sr1 register followed by a write in the dr register with the slave address, holding the scl line low. in standard i2c mode, to guarantee the sart hold time, a software delay must be introduced between set- ting of start bit and writing of dr register with slave address. slave address transmission the slave address is then sent to the sda line via the internal shift register. in 7-bit addressing mode, one address byte is sent. in 10-bit addressing mode, sending the first byte including the header sequence causes the following event: ? the evf bit is set by hardware with interrupt generation if the ite bit is set. then the master waits for a read of the sr1 register followed by a write in the dr register, holding the scl line low. the second address byte is then sent by the interface. after completion of this transfer (and acknowledge from the slave if the ack bit is set): ? the evf bit is set by hardware with interrupt generation if the ite bit is set. then the master waits for a read of the sr1 register followed by a write in the cr register (for example set pe bit), holding the scl line low. next the master must enter receiver or transmitter mode. note: in 10-bit addressing mode, to switch the master to receiver mode, software must generate a re- peated start condition and resend the header sequence with the least significant bit set (11110xx1). master receiver after the address transmission and sr1 and cr registers have been accessed, the master receives bytes from the sda line into the dr register via the internal shift register. after each byte the interface generates in sequence: ? acknowledge pulse if the ack bit is set ? evfand btf bits are set by hardware with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 register followed by a read of the dr register, holding the scl line low. to close the communication: before reading the last byte from the dr register, set the stop bit to generate the stop condition. the interface goes automatically back to slave mode (m/sl bit cleared). note: in order to generate the non-acknowledge pulse after the last received data byte, the ack bit must be cleared just before reading the second last data byte. master transmitter after the address transmission and sr1 register has been read, the master sends bytes from the dr reg- ister to the sda line via the internal shift register. the master waits for a read of the sr1 register fol-lowed by a write in the dr register, holding the scl line low. when the acknowledge bit is received, the interface
stlc1502 44/72 sets: ? evf and btf bits with an interrupt if the ite bit is set. to close the communication: after writing the last byte to the dr register, set the stop bit to generate the stop condition. the interface goes automatically back to slave mode (m/sl bit cleared). error cases berr: detection of a stop or a start condition during a byte transfer. in this case, the evf and berr bits are set by hardware with an interrupt if ite is set. af: detection of a non-acknowledge bit. in this case, the evf and af bits are set by hardware with an interrupt if the ite bit is set. to resume, set the start or stop bit. arlo: detection of an arbitration lost condition. in this case the arlo bit is set by hardware (with an interrupt if the ite bit is set and the interface goes automatically back to slave mode (the m/sl bit is cleared). note: in all these cases, the scl line is not held low; however, the sda line can remain low due to possible ?0? bits transmitted last. it is then necessary to release both lines by software. event flags and interrupt generation diagram figure 17.
45/72 stlc1502 9.7.4 i2c registers map [0x0c300000] the base address of the remap & pause register is 0x0c300000. the offset of any particular register from the base address is the following. table 12. 9.8 uart-universal asynchronous receiver transmitter the uart provides a serial data communication with transmit and receive channels that can operate con- currently to handle a full-duplex operation. two internal fifos for transmitted and received data, deep 16 and wide 8 bits, are present; these fifos can be enabl ed or disabled through a register. interrupts are provided to control reception and transmission of serial data. the clock for both transmit and receive channels is provided by an internal baud rate generator that di- vides its input clock by any divisor value from 1 to 2 16 - 1. 9.8.1 operation the uart supports full-duplex asynchronous communication, where both the transmitter and the receiver use the same data frame format and the same baud rate. data is transmitted on the txd pin and received on the rxd pin. data frames 8-bit data frames either consist of: eight data bits d0-7 (by setting the mode bit field to 001); seven data bits d0-6 plus an automatically generated parity bit (by setting the mode bit field to 011). parity may be odd or even, depending on the parityodd bit in the asccontrol register. an even parity bit will be set, if the modulo-2-sum of the seven data bits is 1. an odd parity bit will be cleared in this case. the parity error flag (parityerror) will be set if a wrong parity bit is received. the parity bit itself will be stored in bit 7 of the ascrx-buffer register. address register name r/w notes i2c_regbase+ 0x20 i2ccr r/w i2c configuration register i2c_regbase+ 0x24 i2csr1 r/w i2c status register 1 i2c_regbase+ 0x28 i2csr2 r/w i2c status register 2. i2c_regbase+ 0x2c i2cccr r/w i2c clock control register. i2c_regbase+ 0x30 i2coar1 r/w i2c own address register i2c_regbase+ 0x34 i2coar2 r/w i2c own address register i2c_regbase+ 0x38 i2cdr r/w i2c data i/o register.
stlc1502 46/72 8-bit data frame 9-bit data frames either consist of: nine data bits d0-8 (by setting the mode bit field to 100) eight data bits d0-7 plus an automatically generated parity bit (by setting the mode bit field to 111) eight data bits d0-7 plus a wake-up bit (by setting the mode bit field to 101) parity may be odd or even, depending on the parityodd bit in the asccontrol register. an even parity bit will be set, if the modulo-2-sum of th e eight data bits is 1. an odd parity bit will be cleared in this case. the parity error flag (parityerror) will be set if a wrong parity bit is received. the parity bit itself will be stored in bit 8 of the ascrx-buffer register. in wake-up mode, received frames are only transferred to the receive buffer register if the ninth bit (the wake-up bit) is 1. if this bit is 0, no receive inte rrupt request will be activated and no data will be transferred. this feature may be used to control communication in multi-processor systems. when the master proces- sor wants to transmit a block of data to one of several slaves, it first sends out an address byte which iden- tifies the target slave. an address byte differs from a data byte in that the additional ninth bit is a 1 for an address byte and a 0 for a data byte, so no slave will be inte rrupted by a data byte. an address byte will interrupt all slaves (operating in 8-bit data + wake-up bit mode), so each slave can examine the 8 least significant bits (lsbs) of the received character (the address). the addressed slave will switch to 9-bit data mode, which enables it to receive the data bytes that will be coming (with the wake-up bit cleared). the slaves that are not being addressed remain in 8-bit data + wake-up bit mode, ignoring the following data bytes. 9-bit data frame 9.8.2 baud rate generation the uart has its own dedicated 16-bit baud rate generator with 16-bit reload capability. the baud rate generator is clocked with the cpu clock. the timer counts downwards and can be started or stopped by the run bit in the asccontrol register. each under-flow of the timer provides one clock pulse. the timer is reloaded with the value stored in its 16-bit reload register each time it underflows. the start bit d0 d1 d2 d3 d4 d5 d6 1st bit stop bit 8th bit stop 2nd -data bit (d7) -parity bit (lsb) start bit d0 d1 d2 d3 d4 d5 d6 1st bit stop bit 9th bit stop 2nd - data bit (d7) - parity bit d7 (lsb) - wake up bit
47/72 stlc1502 ascbaudrate register is the dual-function baud rate generator/reload register. a read from this register returns the content of the timer; writing to it updates the reload register. an auto-reload of the timer with the content of the reload register is performed each time the ascbaudrate register is written to. however, if the run bit is 0 at the time the write operation to the ascbaudrate register is performed, the timer will not be reloaded until the first cpu clock cycle after the run bit is 1. the baud rate generator provides a clock at 16 times the baud rate. the baud rate and the required reload value for a given baud rate can be determined by the following formula: baudrate = fcpu/(16 *ascbaudrate) 9.8.3 the timeout interrupt a timeout counter register provides timeout interrupt on the receive path. whenever the rxfifo has got something in it, the timeout counter will decrement until something happens to the rxfifo. if nothing happens, and the timeout counter reaches zero, the ascstatus(timeoutnotempty) flag will be set. provided ascintenable(timeoutnotempty) is set, this will cause an interrupt. when the software has emptied the rxfifo, the timeout counter will reset and start decrementing. if no more characters arrive, when the counter reaches zero the ascstatus(timeoutidle) flag will be set. provided the ascintenable(timeoutidle) is set, per_interr upt will fire. 9.8.4 interrupt control the uart contains two registers that are used to control interrupts, the status register (ascstatus) and the interrupt enable register (ascintenable). the status bits in the ascstatus register determine the cause of the interrupt. interrupts will occur when a status bit is 1 (high) and the corresponding bit in the ascintenable register is 1. the error interrupt signal is generated by the uart from the or of the parity error, framing error, and overrun error status bits after they have been anded with the corresponding enable bits in the ascinten- able register. an overall interrupt request signal (per_i nterrupt) is generated from the or of the error in- terrupt signal and the txempty, txhalfempty, rxhalffull, rxbuffull signals. note: txfull does not generate interrupt. the status register cannot be written directly by software. the reset mechanism for the status register is described below. txempty, txhalfempty are reset when a character is written to the transmitter buffer. txfull is reset when a character is transmitted rxbuffull and overrunerror are reset when a character is read from the receive fifo. the data error status bits (parityerror, frameerror) are reset when the character with error is read from the receive fifo. 9.8.5 uart memory map the base address of the uart interface is fixed by the apb bridge. table 13. address register name r/w notes uart_regbase+ 0x00 ascbaudrate r/w baud rate generator register uart_regbase+ 0x04 asctxbuffer wo transmit buffer (fifo)
stlc1502 48/72 9.9 gpio/keypad encoder the gpio block is available as a cell that controls 20 input/output pins. the block includes a key scanning encoder. the encoder function is an alternative to the use of 12 i/o pins. the 12 pins are organized as a 6x6 matrix providing an interface to a 36 key keyboard. 16 pins are also multiplexed with the hpi external interface. the hpi interface is selected by external pin hpisel. two pins gpio18, gpio19 are direct in- terrupt sources in the interrupt register when programmed as inputs. the pin description of the gpio pins can be found in the pin description table in section 5.1. 9.9.1 gpio operation mode the gpio operation mode is the parallel port mode. each of the 20 signals may be programmed as an input or an output through a set up register. once pro- grammed, each pin maintains its identity as an input or output. voltages are standard process port levels, 0 and 3.3 volts. the on chip arm processor may read or write to the port at any time. 9.9.2 keyboard operation mode the keyboard may contain up to 36 keys. twelve (12) port pins provide a 6x6 scanning matrix. six of the pins are strobes and six of the pins are inputs. the application circuitry will provide small series resistors to prevent electrostatic damage to the port pins. the circuitry will scan the keys at a rate of 10, 20, 40 or 80 msecs, controlled by the software. two suc- cessive cycles are needed to validate a key. only one key will be allowed down in a scan cycle. once validated as being down, the "no key down" condition must be validated for two complete cycles when the key is released. every valid key condition will cause the value of the key to be written to a register and an interrupt shall be set. two key rollover will not be supported unless the solution is easier to implement than the method described above. 9.9.3 gpio registers map [0x0c400000] the base address of gpio registers is 0x0c400000. the offset of any particular register from the base address is the following. uart_regbase+ 0x08 ascrxbuffer ro receive buffer (fifo). uart_regbase+ 0x0c asccontrol r/w uart control register. uart_regbase+ 0x10 ascintenable r/w uart interrupt enable register uart_regbase+ 0x14 ascstatus ro uart status register. uart_regbase+ 0x18 ascguardtime r/w uart guartime register. uart_regbase+ 0x1c asctimeout r/w uart timeout register. uart_regbase+ 0x20 asctxreset wo flush transmit buffer (fifo) uart_regbase+ 0x24 ascrxreset wo flush receive buffer (fifo) address register name r/w notes
49/72 stlc1502 table 14. 9.10 hpi (*) the hpi is dual port sram based, with control that generates an interrupt when a message is sent. the dpram is implemented on chip and has a message buffer size of 256 bytes for each direction. input buffer is used for messages from host processor to stradivarius. output buffer is used for messages from stradivarius to host processor. the external bus interface of the hpi is compatible with motorola mpc850 network processor. the data bus width is 8 bits. a status register, an index register (for the host processor), an interrupt mask register, and a mes- sage buffer are required for both input and output transactions. the input status register (isr) is set by the host processor by writing 0x01 and cleared by writing 0x00 to the location. it is cleared by arm by writing anything to it. the output status registers (osr) is set by the arm by writing 0x01 and cleared by writing 0x00. it is cleared by the host processor by writing anything to it. the input and output index registers (iir & oir respectively) are reset to their starting value by writ- ing 0x00 to their respective addresses. they can also be cleared by the host processor by writing anything to them. the input interrupt mask register (iim) resets to 0x00, causing the mask to be set (active low). this means that before the arm can receive message ready interrupts from the host processor, this reg- ister must be written with 0x0001 (by arm) to unmask the interrupt. the output interrupt mask register (oim) resets to 0x00, causing the mask to be set (active low). this means that before the host processor can receive message ready interrupts from the arm, this register must be written with 0x01 (by the host processor) to unmask the interrupt. the input and output message buffers are each 256 bytes long and 1 byte wide (an overflow in the index register will not write to the other message buffer, but will start to overwrite the current mes- sage buffer). addressing of the input and output message buffers by the host processor is implemented indirectly via the input and output index registers. an exte rnal interrupt signal is generated when the output status register is set by the arm7. an arm7 interrupt signal is generated when the input status reg- ister is set by the host processor. (*) note: hpi interface is available only on request address register name r/w notes gpio_regbase+ 0x00 control r/w this register allows to set the block functionality gpio_regbase+ 0x04 mask w this register allows gpio direction setting (output enable) gpio_regbase+ 0x08 data r/w this register allows gpio data output setting gpio_regbase+ 0x0c status r/w key data flag gpio_regbase+ 0x10 key r key value
stlc1502 50/72 9.10.1 send message from host processor to arm read input status register. if h01, the arm has not read out the last message. if 0x00, the arm has read the last message and the input message buffer is available for use. clear input index reg by writing any value to its address (b.100). write message into input message buffer by consecutively writing to its address (b.111). each write will cause the i nput index register to increment by 1 and access another byte location. write 0x01 to input status register (address b.011) to interrupt the arm 9.10.2 receive message from arm by host processor after receiving interrupt from arm: clear output index register (address b.001) by writing any value. read message from output message buffer by consecutively reading from its address (b.110). each read will cause the output index register to increment by 1 and access another byte location. clear the output status reg (address b.000) by writing any value (the arm can clear the osr by writing 0 to it). 9.10.3 send message from arm to host processor read output status register. if h0001, the hp has not read out the last message. if 0x0000, the hp has read the last message and the output message buffer is available for use. write message into output message buffer. this buffer is directly addressable by the arm. write 0x0001 to output status register to interrupt the hp 9.10.4 receive message from host processor by arm after receiving interrupt from hp: read message from input message buffer.this buffer is directly addressable by the arm. clear the input status reg by writing 0x0001 to its address (the hp can clear the isr by writing 0 to it). in the following table there is the list of the available external signals of the hpi interface. table 15. external signals of hpi name signal type description hpi_clk in hpi bus clock form host processor hpi_cs in active low select from host processor. hpi_as in address strobe from host processor. hpi_r w in r/w from host processor hpi_addr(2:0) in host processor address hpi_data(7:0) inout host processor data bus lines. hp_int out interrupt to host processor
51/72 stlc1502 9.10.5 hpi memory map 9.11 dual port sram a dual port sram 4096x16 connected between the apb bus and the x bus of the d950 domain, is used as a mailbox between the arm7 and the d950. the dpram can be written/read everywhere by both the arm and the d950. the dpram bank has two status sections consisting of 32, 16 bits memory locations, and a message section consisting 4064 16 bit memory locations. there are 4 hardware registers: arm and d950 mailbox mask registers and arm and d950 mailbox registers. mailbox registers: the writing of any value in a status location will set the corresponding bit in the mailbox to 1. this will generate an interrupt if the corresponding mailbox m ask register bit is set to 1, and won?t if the bit is set to 0. reading a st atus location will clear th e corresponding bit in the mailbox to 0. (note: only the arm can clear the d950 mailbox on a read, and only the d950 can clear the arm mailbox on a read. likewise only the arm can set the arm mailbox bits by writing to the arm status registers, and only the d950 can set the d950 mailbox by writing to the d950 sta- tus registers). mailbox mask registers: writing 0 in a bit location will allow the status location to set the corre- sponding bit in the mailbox, but will mask out the generation of an interrupt. the mailbox mask registers are both reset to all 0?s, so, by default, no interrupts will be generated. 9.11.1 dpram protocol there can be up to 16 different communication channels that the d950 and the arm can use to exchange mes- sages between them. the allocation of the 4064 addressable message buffers locations in the dpram is com- pletely under the programmer?s control. there is no intervention by the hardware on the dpram other than use the first 32 locations to set and clear the mailbox registers and ultimately generate interrupts. a software pro- tocol must be established in advance to safely pass messages. every time one of the two devices wants to write or receive a message, it should follow the example protocol here below, where the d950 sends a message to the arm. the same apply in the reverse direction with arm and d950 side swapped. table 16. register map of the dport peripheral register name arm 7 address host processor addr. output status reg hpi_regbase +0x0c00 0x0 output index reg hpi_regbase +0x0c02 0x1 output mask reg hpi_regbase +0x0c04 0x2 input status reg hpi_regbase +0x0c06 0x3 input index reg hpi_regbase +0x0c08 0x4 input mask reg. hpi_regbase +0x0c0a 0x5 output message buffer hpi_regbase +0x0000 - hpi_regbase +0x01fe 0x6 output message buffer hpi_regbase +0x0200 - hpi_regbase +0x03fe 0x7
stlc1502 52/72 the d950 reads the d950 mailbox register bit corresponding to the channel it wants use for the message. if it is set to 1, the previous message has not been read by the arm and the channel is not available. if the content of that bit is 0, then the d950 can write the message for the arm into the appropriate section of the dpram the d950 writes any value in the appropriate d950_status_x location (0<= x<= 15), indicating that the message has just been put in the dpram. this will cause the corresponding bit in the d950 mailbox register to be set to 1. if the corresponding bit in the d950 mailbox mask register is set to 1, then an interrupt request for the arm will be gener ated. the interrupt line is the logical or of all the unmasked bits in the d950 mail- box register. the arm interrupt service routi ne will read th e d950 mailbox register and compare this with the d950 mailbox m ask register to determine which c hannel caused the interrupt. the arm reads the appropriate section of the dpram. when it has finished reading the message, it reads the corresponding d950 status location. this latest read clears the corresponding bit in the d950 mailbox register. if no other unmasked bits are set in the d950 mailbox register, the arm interrupt clears, otherwise remains set. multiple channels can be used concurrently. it is up to the receiver to manage this eventuality. so the dpram can be used to buffer the messages as it is processed, while other channels are still availa- ble for communication.
53/72 stlc1502 9.11.2 dual port memory map [0x0c180000] the base address of the dual port memory is 0x0c180000. the base address of control registers is 0x0c188000 the dpram is mapped in the arm memory space as shown below: figure 18. dpram memory map dpcomm 0c180000 0c181fff arm_status_0 0c184000 arm_status_1 0c184004 arm_status_2 0c184008 arm_status_3 0c18400c d950_status_15 0c18407c arm_status_15 0c18403c d950_status_0 0c184040 d950_status_1 0c184044 d950_status_2 0c184048 dpram reserved 0c180000 0c1803fe (4096x16) reserved control 0c188000 0c18800c registers reserved 0c181fff
stlc1502 54/72 9.11.3 dpram registers map table 17. 10 stlc1502 register map following is the complete list and the description of every peripheral register of the stlc1502 table 18. address register name r/w notes dport_regbase+ 0x0 d950_mailbox r it contains the pending interrupt requests that notify to the arm has a message coming from the d950 to read. there is an interrupt line for each message class dport_regbase+ 0x4 d950_mailbox_mask r/w it contains the mask for the d950_mailbox dport_regbase+ 0x8 arm_mailbox r it contains the pending interrupt requests that notify to the d950 has a message coming from the arm to read. there is an interrupt line for each message class dport_regbase+ 0xc arm_mailbox_mask r it contains the mask for the arm_mailbox address register name r/w note 0x0c000000 timer1load r/w timer block register 0x0c000004 timer1value r timer block register 0x0c000008 timer1control r/w timer block register 0x0c00000c timer1clear w timer block register 0x0c000010 timer2load r/w timer block register 0x0c000014 timer2value r timer block register 0x0c000018 timer2control r/w timer block register 0x0c00001c timer2clear w timer block register 0x0c000020 timer3load r/w timer block register 0x0c000024 timer3value r timer block register 0x0c000028 timer3control r/w timer block register 0x0c00002c timer3clear w timer block register 0x0c000030 timer4load r/w timer block register
55/72 stlc1502 0x0c000034 timer4value r timer block register 0x0c000038 timer4control r/w timer block register 0x0c00003c timer4clear w timer block register 0x0c080000 control w miscellaneous 0x0c080004 status w miscellaneous 0x0c080008 identification r miscellaneous 0x0c100000 irqstatus r interrupt control 0x0c100004 irqrawstatus r interrupt control 0x0c100008 irqenableset r/w interrupt control 0x0c10000c irqsoft w interrupt control 0x0c100010 fiqstatus r interrupt control 0x0c100014 fiqrawstatus r interrupt control 0x0c100018 fiqenableset r/w interrupt control 0x0c10001c irqenableclear w interrupt control 0x0c100020 fiqenableclear w interrupt control 0x0c100024 irqtestsourcet r/w interrupt control 0x0c100028 irqsourcesel r/w interrupt control 0x0c10002c fiqtestsource r/w interrupt control 0x0c100030 fiqsourcesel r/w interrupt control 0x0c188000 d950_mailbox r dport 0x0c188004 d950_mailbox_mask r/w dport 0x0c188008 arm_mailbox r dport 0x0c18800c arm_mailbox_mask r dport 0x0c280004 spidr r/w spi data i/o register. 0x0c280008 spicr r/w spi configuration register 0x0c28000c spisr r/w spi status register 0x0c300020 i2ccr r/w i2c configuration register address register name r/w note
stlc1502 56/72 0x0c300024 i2csr1 r/w i2c status register 1 0x0c300028 i2csr2 r/w i2c status register 2. 0x0c30002c i2cccr r/w i2c clock control register. 0x0c300030 i2coar1 r/w i2c own address register 0x0c300034 i2coar2 r/w i2c own address register 0x0c300038 i2cdr r/w i2c data i/o register. 0x0c380000 ascbaudrate r/w uart baud rate register 0x0c380004 asctxbuffer wo uart transmit buffer (fifo) 0x0c380008 ascrxbuffer ro uart receive buffer (fifo). 0x0c38000c asccontrol r/w uart control register. 0x0c380010 ascintenable r/w uart interrupt enable register 0x0c380014 ascstatus ro uart status register. 0x0c380018 ascguardtime r/w uart guartime register. 0x0c38001c asctimeout r/w uart timeout register. 0x0c380020 asctxreset wo flush transmit buffer (fifo) 0x0c380024 ascrxreset wo flush receive buffer (fifo) 0x0c480000 control r/w gpio/kybd 0x0c480004 mask w gpio/kybd 0x0c480008 data r/w gpio/kybd 0x0c48000c status r/w gpio/kybd 0x0c480010 key r gpio/kybd 0x0c480000 output status reg ro hpi output buffer status register 0x0c480004 output index reg r/w hpi output buffer index register 0x0c480008 output mask reg r/w hpi output interrupt mask 0x0c48000c input status reg ro hpi input buffer status register 0x0c480010 input index reg r/w hpi input buffer index register 0x0c480014 input mask reg. r/w hpi input interrupt mask 0x0c480800 output message buffer wo hpi output buffer register address register name r/w note
57/72 stlc1502 11 d950 domain the d950 domain consists of a d950 core, i ram, i rom, x ram, y ram, timer, emulator, interrupt controller and tap, pcm interface peripherals. 0x0c480c00 input message buffer ro hpi input buffer register 0x0c500000 wdtcontrol r/w wdt control register 0x0c500004 wdt reset_stat r/w wdt reset the status register 0x0c500008 wdt max_count r/w wdt programmable max count 0x0c50000c wdt counter r wdt internal counter value 0x0c600000 mb1config r/w edm bank 1 configuration 0x0c600004 mb2config r/w edm bank 2 configuration 0x0c600008 mb3config r/w edm bank 3 configuration 0x0c60000c mb4config r/w edm bank 4 configuration 0x0c600010 sdram1configlo wo edm bank 1 low sdram 0x0c600014 sdram1confighi wo edm bank 1 high sdram 0x0c600018 sdram2configlo wo edm bank 2 low sdram 0x0c60001c sdram2confighi wo edm bank 2 high sdram 0x0c600020 sdram3configlo wo edm bank 3 low sdram 0x0c600024 sdram3confighi wo edm bank 3 high sdram 0x0c600028 sdram4configlo wo edm bank 4 low sdram 0x0c60002c sdram4confighi wo edm bank 4 high sdram 0x0c600030 memconfig r/w edm configuration register 0x0c600000 cs0 r/w static esm_ cs0 bank control 0x0c600004 cs1 r/w static esm_cs1 bank control 0x0c600008 cs2 r/w static esm_cs2 bank control address register name r/w note
stlc1502 58/72 11.1 d950 memory map the following table provides the memory map of d950 on x, y, i buses. table 19. mapping of d950 y memory space (1 word = 16 bit) table 20. mapping of d950 x memory space (1 word = 16 bit) table 21. address area name area size 0x0000 --------- 0x000f dsp registers 16 words 0x0010 ------- 0x001f emu 16 words 0x0020 ------- 0x002f itc 16 words 0x0030 ------- 0x005f reserved dsp 0x0060 ------- 0x006f tim 16 words 0x0070 ------- 0xffff ram y 64 kwords address area name area size 0x0000 --------- 0x7fff ram x 32 kwords 0x8000 ------- 0xbfff dpcom 16 kwords 0xc000 ------- 0xffff pcmif 16 kwords address area name area size 0x0000 --------- 0x3fff rom i (first bank) 16 kwords
59/72 stlc1502 mapping of d950 i memory space (1 word = 16 bit) 11.2 dpram memory map [0x8000] the base address of the dpram is 0x8000 in the x memory space. the base address of control registers is 0xa800 in the x memory space for a description of dpram protocol refer to the dpram section in the arm domain. figure 19. 0x4000 ------- 0x7fff rom i (second bank) 16 kwords 0x8000 ------- 0xbfff rom i (third bank) 16 kwords 0xc000 ------- 0xffff ram i 16 kwords address area name area size dpcomm 8000 bfff arm_status_0 a000 arm_status_1 a001 arm_status_2 a002 arm_status_3 a003 d950_status_15 a01f arm_status_15 a00f d950_status_0 a010 d950_status_1 a011 d950_status_2 a012 dpram reserved 8000 8fff (4096x16) reserved control a800 a803 registers reserved bfff
stlc1502 60/72 table 22. 12 pcm interface the pcm interface is used to actually send and receive voice samples. on the other side, the pcm block has an interface to the d950 xbus. moreover two other signals to feed the master clock and the hardware reset are present. figure 20. pcm-block interconnection scheme address register name r/w notes dport_regbase+ 0x0 arm_mailbox r it contains the pending interrupt requests that notify to the d950 has a message coming from the arm to read. there is an interrupt line for each message class dport_regbase+ 0x1 arm_mailbox_mask r/w it contains the mask for the arm_mailbox dport_regbase+ 0x2 d950_mailbox r it contains the pending interrupt requests that notify to the arm has a message coming from the d950 to read. there is an interrupt line for each message class dport_regbase+ 0x3 d950_mailbox_mask r it contains the mask for the d950_mailbox dr dx pclk pfs pcm xae(15:0) xde(15:0) xwren xrden xbsen itr3n itr7n rstn clk d950 misc
61/72 stlc1502 the pcm interface has 5 main signals: dr (output): this is the serial data stream that the pcm sends to the codec dx (input): this is the serial data stream sent by the codec and received by the pcm block pclk (input/output): this is the pcm clock sent to codec. in the application, the frequency is 2.048mhz. the pcm clock can be generated by the pcm block from internal master clock or can be input externally, according to the bit clken in configuration register pfs (input/output): this signal is asserted high when the frame number zero is present on the serial data stream; it is possible to program the codec so that the pcm block asserts this signal on a given frame (fs). the same frame number is always present in the same time on dr and dx. the pfs can be generated by division from pclk or can be input externally, according to fsen in the config- uration register. 12.1 miscellaneous interface this interface has two signals: rstn (input): this is the hardware active low reset clk (input): this is the master input clock coming from the external oscillator at 2. 048mhz in the cur- rent application. 12.2 interrupt event management there are two interrupt lines that goes to the d950. itr3 line (overrun) itr7 line (frame synch). figure 21. interrupt block pcm_interrupt_mask enable d950 itr3 other interrupt bit slices pcm_interrupt pcm_interrupt_row interrupt source interrupt pending
stlc1502 62/72 12.3 clock distribution the pcm block works at 2.048mhz clock and it is a fully synchronous design at that frequency. no gated clock, no latches are used. the design is able to support also higher pcm hierarchies such as 4.096mhz and 8.196mhz. the d950 interface works as a clock stage decoupling block. it can be accessed externally at 66mhz, while internally it works at 2.048mhz. 12.4 reset distribution and configuration the pcm block has an explicit active low reset pin controlled by arm. a software reset is implemented in the pcm_configuration register at the address 0x0002. in the pcm_configuration register there is also a bit that configures the fpga itself as linear or pcm coding. 12.5 data flow management per each direction the pcm block contains a double buffer used to store and forward the voice samples. this has to be big enough to store all (four) voice samples coming (and going) from (to) the slics contained in one pcm frame. actually the number of bits per voice channel per pcm frame is 8 in case of pcm coding (a low or u low) and 16 in case of linear coding. other bits are used to provide information about the number of the logic channel the frame is associated with. so, it is necessary to have two memory banks per direction. for example, in the upstream direction (from the codec to the d950), one bank is used to store the incoming voice samples (on-line bank) and the other used to keep the voice samples received in the previous pcm frame (off-line bank) while they are read by the d950. this mechanism is needed because the pcm flow is synchro- nous and cannot be stopped. the memory banks are swapped between them on pcm frame basis; so while the incoming information is writ- ten in the on-line memory, the d950 can read the information contained in the previous pcm frame from the off- line memory bank. every pcm frame (fs signal based) the on-line memory becomes off-line and viceversa. this swap is transparent for the d950 so that the d950 sees the two memory banks located always at the same addresses. the same scheme in a different hardware block implements the memory buffer for the downstream flow (from the d950 to the codec). 12.6 basic operation the pcm block uses the reference clock to generate an internal time base. for example, it generates the fs signal with the proper timing. then an internal register has to store the association between the voice channel (slic) and the pcm slots according to the configuration of the codec (dra# and dxa# registers). the fs signal is sent not only to the codec, but also to the d950 (through itr7), in order to give it the proper timing reference. so, between two subsequent fs signals, the d950 has to read back from the pcm block the voice samples of the previous pcm frame and has to write in it the pcm samples of the several voice channels that the pcm block itself will send to the codec in the following pcm frame. so the itr7 is an 8khz interrupt signal that provides the timing reference to the d950.
63/72 stlc1502 12.7 pcm coding voice frame this section describes the operation of the pcm block in case of pcm coding of the voice samples (lin bit of the codec conf register set to 0x0). in this case each voice sample has 8 bits, plus 3 miscellaneous bits per channel. so a total of 2 direction x 2 banks x 4 channels x 11 bits each (176 bits) are needed. this memory is implemented internally in the pcm block. the pcm_voice_frame_from_codec_x (x=0..3) and the pcm_voice_frame_to_codec_x (x=0..3) are used to store upstream and downstream voice channel x. selection between pcm and linear coding is done in the pcm_configuration register pcm coding upstream basic operation (from the codec to the d950) the pcm voice samples coming from the codec are inserted in the on-line upstream memory. in the same pcm slot, the d950 accesses at the off-line upstream memory through the pcm_voice_frame_from_codec_x register connected to off-line memory. if during a pcm frame, the d950 left some unread voice data in the off- line memory (in the meantime became on-line) an interrupt even is generated (ov_u bit of the pcm_interrupt register). 12.7.1 linear coding voice frame if the linear coding (lin bit of the codec conf register set to 0x1) is selected, each voice sample is coded as a 16 bit two?s complement. this means that each voice channel takes two pcm slot to transport the voice infor- mation. for example, considering the channel x (x=0..3), for the upstream flow (voice sample from the codec to the d950), the 8 most significant bits are transported in the pcm slot reported in the pcm_slot_up field of the pcm_slot_from_codec_x register while 8 less significant bits are transported in the following at reset pcm_lin_data_down=0x0000. x values: 0..3. 12.8 pcm register list this section reports the list of the pcm block registers in the d950 domain. the address is referred to the base address where the pcm block is placed on. in other words, they are displacement addresses. the d950 cannot access the arm7 memory space. table 23. register list address register name description 0x0000 pcm_reset reset register 0x0001 n/a 0x0002 n/a 0x0003 n/a 0x0004 pcm_slot_from_codec_0 upstream pcm slot register for voice channel 0 0x0005 pcm_slot_from_codec_1 upstream pcm slot register for voice channel 1 0x0006 pcm_slot_from_codec_2 upstream pcm slot register for voice channel 2 0x0007 pcm_slot_from_codec_3 upstream pcm slot register for voice channel 3
stlc1502 64/72 0x0008 pcm_slot_to_codec_0 downstream pcm slot register for voice channel 0 0x0009 pcm_slot_to_codec_1 downstream pcm slot register for voice channel 1 0x000a pcm_slot_to_codec_2 downstream pcm slot register for voice channel 2 0x000b pcm_slot_to_codec_3 downstream pcm slot register for voice channel 3 0x000c pcm_interrupt interrupt 0x000d pcm_interrupt_mask interrupt mask 0x000e pcm_interrupt_row interrupt row 0x000f n/a 0x0010 pcm_voice_frame_from_codec_0 upstream voice sample register for channel 0 0x0011 pcm_voice_frame_from_codec_1 upstream voice sample register for channel 1 0x0012 pcm_voice_frame_from_codec_2 upstream voice sample register for channel 2 0x0013 pcm_voice_frame_from_codec_3 upstream voice sample register for channel 3 0x0014 pcm_voice_frame_to_codec_0 downstream voice sample register for channel 0 0x0015 pcm_voice_frame_to_codec_1 downstream voice sample register for channel 1 0x0016 pcm_voice_frame_to_codec_2 downstream voice sample register for channel 2 0x0017 pcm_voice_frame_to_codec_3 downstream voice sample register for channel 3 0x0018 pcm_lin_voice_frame_from_codec_0 upstream linear voice sample register for ch 0 0x0019 pcm_lin_voice_frame_from_codec_1 upstream linear voice sample register for ch1 0x001a pcm_lin_voice_frame_from_codec_2 upstream linear voice sample register for ch 2 0x001b pcm_lin_voice_frame_from_codec_3 upstream linear voice sample register for ch 3 0x001c pcm_lin_voice_frame_to_codec_0 downstream linear voice sample register for ch 0 0x001d pcm_lin_voice_frame_to_codec_1 downstream linear voice sample register for ch 1 0x001e pcm_lin_voice_frame_to_codec_2 downstream linear voice sample register for ch 2 0x001f pcm_lin_voice_frame_to_codec_3 downstream linear voice sample register for ch 3 address register name description
65/72 stlc1502 13 electrical specifications and timings table 24. absolute maximum ratings table 26. general ac specifications parameter value supply voltage(vcc) -0.5 v to 7.0 v input voltage -0.5 v to vcc + 0.5 v output voltage -0.5 v to vcc + 0.5 v storage temperature -65 c to 150 c(-85 f to 302 f) ambient temperature 0 c to 70 c(32 f to 158 f) esd protection 2000v table 25. general dc specifications symbol parameter test condition min. typ. max. units general dc vdd3 supply voltage 3.15 3.3 3.45 v vdd core supply voltage 2.35 2.5 2.65 v idd3 operating current 70 ma idd operating current 170 ma voltage/current characteristics v il input low level 00.2vddv v ih input high level 0.8vdd vdd v v ol output low level 0.4 v v oh output high level 0.85vdd v symbol parameter test condition min. typ. max. units arm ac characteristics tmckl mclk low time 15.1 ns tmckh mclk high time 15.1 ns tws nwait setup to mclkr 2.3 ns twh nwait hold from ckf 1.1 ns taddr mclkr to address valid 14.0 ns
stlc1502 66/72 figure 22. arm mclk timing characteristics tmsd mclkf to nmreq & seq valid 17.9 ns tah address hold time from mclkr 2.4 symbol parameter test condition min. typ. max. units trwd mclkr to nrw valid 14.0 trwh nrw hold time from mclkr 2.4 tcdel mclk to eclk delay 2.9 trstl nreset low for guaranteed reset 2 mclk cycles d950 ac characteristics t0 master clock cycle time 7.5 ns t3 clkout high delay 4.0 ns t4 clkout low delay 3.3 ns t5 incycle high delay -0.1 ns t6 incycle low delay -0.5 ns
67/72 stlc1502 figure 23. d950 clock timing diagram figure 24. general arm timings table 27. mii management clock timing specifications t1 mdc low pulse width 200 ? ns t2 mdc high pulse width 200 ? ns t3 mdc period 400 ? ns t4 mdio(i) setup to mdc rising edge 10 ? ns t5 mdio(o) hold time from mdc rising edge 10 ? ns t6 mdio(o) valid from mdc rising edge 0 300 ns
stlc1502 68/72 mii management clock timing figure 25. table 28. mii receive timing specification symbol parameter test condition min. typ. max. units t1 rx-er, rx-dv, rxd[3:0] setup to rx- clk 10 ? ns t2 rx-er, rx-dv, rxd[3:0] hold after rx- clk 10 ? ns t3 rx-clk high pulse width (100 mbits/s) 14 26 ns rx-clk high pulse width (10 mbits/s) 200 ns t4 rx-clk low pulse width (100 mbits/s) 14 26 ns rx-clk low pulse width (10 mbits/s) 140 260 ns t5 rx-clk period (100 mbits/s) 40 ns rx-clk period (10 mbits/s) 400 ns
69/72 stlc1502 mii receive timing figure 26. table 29. mii transmit timing specification mii transmit timing figure 27. symbol parameter test condition min. typ. max. units t1 tx-er,tx-en,txd[3:0] setup to tx-clk rise 10 ? ns t2 tx-er,tx-en,txd[3:0] hold after tx-clk rise 025ns
stlc1502 70/72 figure 28. pqfp208 mechanical data & package dimensions dim. mm inch min. typ. max. min. typ. max. a 4.10 0.161 a1 0.25 0.010 a2 3.40 3.20 3.60 0.134 0.126 0.142 b 0.17 0.27 0.007 0.011 c 0.09 0.20 0.003 0.008 d 30.60 1.205 d1 28.00 1.102 d3 25.50 1.004 e 0.50 0.020 e 30.60 1.205 e1 28.00 1.102 e3 25.50 1.004 l 0.45 0.60 0.75 0.018 0.024 0.029 l1 1.30 0.051 k 0 (min.), 3.5 (typ.), 7 (max.) pqfp208 a a2 a1 b c 52 53 104 105 156 157 208 e3 d3 e1 e d1 d e 1 k b pqfp208m l l1 gage plane 0.25mm .010 pin1 identification seating plane 0.076mm .003inch exact shape of each corner is optional outline and mechanical data
71/72 stlc1502 table 30. revision history date revision description of changes may 2004 1 first issue august 2004 2 changed the address of the status and identification register name in the table 9 and table 18.
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ddx is a trademark of apogee tecnology inc. ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com 72/72 stlc1502

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